Pre-Lab A BCD-to-seven-segment decoder is a combinational circuit that converts

Question

Pre-Lab A BCD-to-seven-segment decoder is a combinational circuit that converts a 4-bit representation of a decimal digit (BCD to a 7-bit output that is used to light the segments in a 7-segment display arranged as shown in the figure below. That is, the output of this circuit is used to display the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d, e,f. g) select the corresponding LEDs in the display, as shown in figure below lay chosen to represent the decimal digit is shown as well. (a) Segment designation (b) Numerical designation for display 1. Write the truth table relating the four binary inputs to the 7 LED outputs of the BCD-to-seven-segment decoder (assume Active-High signals). DO NOT use K-Maps, as there no need for equations. Draft the Verilog code using behavioral modeling. Use a Case Statement relating the binary number input to it seven-segment representation (pattern) 2. Draft the arithmetic statement (in Dataflow or Behavioral) for a 3-bit adder. Don't forget to properly de- fine the input and sum registers.

Explanation / Answer

// Part A) Seven segment module
module sevensegment(bcd_input, a, b, c, d, e, f, g);
input [3:0] bcd_input;
output a, b, c, d, e, f, g;
//internal wire signal
wire [6:0] segment_out1;
always @(bcd_input)
begin
case(bcd_input)
4'd0 : segment_out1 = 7'b111_1110; // represents 0 in SSD
4'd1 : segment_out1 = 7'b011_0000; // represents 1 in SSD
4'd2 : segment_out1 = 7'b110_1101; // represents 2 in SSD
4'd3 : segment_out1 = 7'b111_1001; // represents 3 in SSD
4'd4 : segment_out1 = 7'b011_0011; // represents 4 in SSD
4'd5 : segment_out1 = 7'b101_1011; // represents 5 in SSD
4'd6 : segment_out1 = 7'b101_1111; // represents 6 in SSD
4'd7 : segment_out1 = 7'b111_0000; // represents 7 in SSD
4'd8 : segment_out1 = 7'b111_1111; // represents 8 in SSD
4'd9 : segment_out1 = 7'b111_1011; // represents 9 in SSD
default : segment_out1 = 7'b111_1110; // represents 0 in SSD
endcase
end
  
// assignment of the output from internal signal
assign {a, b, c, d, e, f, g} = segment_out1;

/////// TRUTH TABLE FOR SEVEN SEGMENT DISPLAY ////////////
//=========================================================
//|| BCD input || a | b | c | d | e | f | g |
//=========================================================
//|| 0 || 1 | 1 | 1 | 1 | 1 | 1 | 0 |
//|| 1 || 0 | 1 | 1 | 0 | 0 | 0 | 0 |
//|| 2 || 1 | 1 | 0 | 1 | 1 | 0 | 1 |
//|| 3 || 1 | 1 | 1 | 1 | 0 | 0 | 1 |
//|| 4 || 0 | 1 | 1 | 0 | 0 | 1 | 1 |
//|| 5 || 1 | 0 | 1 | 1 | 0 | 1 | 1 |
//|| 6 || 1 | 0 | 1 | 1 | 1 | 1 | 1 |
//|| 7 || 1 | 1 | 1 | 0 | 0 | 0 | 0 |
//|| 8 || 1 | 1 | 1 | 1 | 1 | 1 | 1 |
//|| 9 || 1 | 1 | 1 | 1 | 0 | 1 | 1 |
//=========================================================

endmodule


//Part B)
module adder_3bit (A, B, Cin, Sum, Cout);
input [2:0] A;
input [2:0] B;
input Cin;

// 3 bit Adder using behavioural code  
assign {Cout, Sum} = A + B + Cin;

endmodule

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