The processor needs to compute the next PC after each instruction. Write a veril
ID: 3349648 • Letter: T
Question
The processor needs to compute the next PC after each instruction. Write a verilog module which computes the next PC. Be sure to include the B (branch), and CBZ (compare-and-branch-on-zero) cases. You may use the output “control” module as shown in the figure in the previous problem. Figure from previous problem module NextPClogic(NextPC, CurrentPC, SignExtlmm64, Branch, ALUZero, Uncondbranch): input (63:0] CurrentPC, SignExtlmm64; input Branch, ALUZero, Uncondbranch; output (63:0] NextPC; " write your code here "/ endmoduleExplanation / Answer
module getNextPC (PCSrc, currPC, offset, out);
parameter MIPS_PC_WIDTH_m1 = 7;
input PCSrc;
input [MIPS_PC_WIDTH_m1:0] offset;
input [MIPS_PC_WIDTH_m1:0] currPC;
output reg [MIPS_PC_WIDTH_m1:0] out;
always @(PCSrc, currPC, offset)
if (PCSrc == 0)
out <= currPC + 1;
else
out <= currPC + 1 + offset;
endmodule
module MIPSALU (ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output reg [31:0] ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
always @(ALUctl, A, B) //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1:0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0; //default to 0, should not happen;
endcase
endmodule
module SignExtend (in, out);
input [31:0] in;
output [64:0] out;
assign out[31:0] = in[31:0];
assign out[64:31] = in[31];
endmodule
module STwoToOne32 (sel, in0, in1, out);
input sel;
input [64:0] in0, in1;
output reg [64:0] out;
always @(sel, in0, in1)
if (sel == 0)
out <= in0;
else
out <= in1;
endmodule
module getNextPC (PCSrc, currPC, offset, out);
parameter MIPS_PC_WIDTH_m1 = 7;
input PCSrc;
input [MIPS_PC_WIDTH_m1:0] offset;
input [MIPS_PC_WIDTH_m1:0] currPC;
output reg [MIPS_PC_WIDTH_m1:0] out;
always @(PCSrc, currPC, offset)
if (PCSrc == 0)
out <= currPC + 1;
else
out <= currPC + 1 + offset;
endmodule
module MIPSALU (ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output reg [31:0] ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
always @(ALUctl, A, B) //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1:0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0; //default to 0, should not happen;
endcase
endmodule
module SignExtend (in, out);
input [31:0] in;
output [64:0] out;
assign out[31:0] = in[31:0];
assign out[64:31] = in[31];
endmodule
module STwoToOne32 (sel, in0, in1, out);
input sel;
input [64:0] in0, in1;
output reg [64:0] out;
always @(sel, in0, in1)
if (sel == 0)
out <= in0;
else
out <= in1;
endmodule
module getNextPC (PCSrc, currPC, offset, out);
parameter MIPS_PC_WIDTH_m1 = 7;
input PCSrc;
input [MIPS_PC_WIDTH_m1:0] offset;
input [MIPS_PC_WIDTH_m1:0] currPC;
output reg [MIPS_PC_WIDTH_m1:0] out;
always @(PCSrc, currPC, offset)
if (PCSrc == 0)
out <= currPC + 1;
else
out <= currPC + 1 + offset;
endmodule
module MIPSALU (ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output reg [31:0] ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
always @(ALUctl, A, B) //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1:0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0; //default to 0, should not happen;
endcase
endmodule
module SignExtend (in, out);
input [31:0] in;
output [64:0] out;
assign out[31:0] = in[31:0];
assign out[64:31] = in[31];
endmodule
module STwoToOne32 (sel, in0, in1, out);
input sel;
input [64:0] in0, in1;
output reg [64:0] out;
always @(sel, in0, in1)
if (sel == 0)
out <= in0;
else
out <= in1;
endmodule
module getNextPC (PCSrc, currPC, offset, out);
parameter MIPS_PC_WIDTH_m1 = 7;
input PCSrc;
input [MIPS_PC_WIDTH_m1:0] offset;
input [MIPS_PC_WIDTH_m1:0] currPC;
output reg [MIPS_PC_WIDTH_m1:0] out;
always @(PCSrc, currPC, offset)
if (PCSrc == 0)
out <= currPC + 1;
else
out <= currPC + 1 + offset;
endmodule
module MIPSALU (ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output reg [31:0] ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
always @(ALUctl, A, B) //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1:0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0; //default to 0, should not happen;
endcase
endmodule
module SignExtend (in, out);
input [31:0] in;
output [64:0] out;
assign out[31:0] = in[31:0];
assign out[64:31] = in[31];
endmodule
module STwoToOne32 (sel, in0, in1, out);
input sel;
input [64:0] in0, in1;
output reg [64:0] out;
always @(sel, in0, in1)
if (sel == 0)
out <= in0;
else
out <= in1;
endmodule
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.