Question
For questions 1 through 6, refer to the preliminary pipeline design, shown below, which supports execution of the following MIPS instructions: add, sub, and, or, slt, lw, sw, beq and . For all questions, assume that the individual stages of the datapath have the following latencies (different from the course notes): What would be the minimum clock cycle time for this datapath, if it were not Pipelined? Why? What would be the minimum clock cycle time for this datapath, if it were pipelined? Why? What would be the total latency for the beq instruction if the datapath were not pipelined? Why? What would be the total latency for the beq instruction if the datapath were pipelined? Why? Suppose that you could split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage. Which stage would you split, what would be the new minimum clock cycle time, and what would be the total latency for the new pipeline? For this questions, assume that instructions executed are broken down as follows and the pipelined datapath described above is used: Assuming there are no stalls or hazards, what is the utilization (% of cycles actually used, not merely present) of the data memory? Assuming there are no stalls or hazards, what is the utilization of the write-register port of the register file? Assuming there are no stalls or hazards, what is the utilization of the add unit in the EX stage? For this question, assume we have the 5-stage pipelined datapath described above, with the necessary interstage buffers, but with no forwarding or hazard detection hardware. Consider executing the following sequence of instructions on such a datapath: Identify all of the data hazards that are present in the given sequence of instructions. State the numbers of the leading and following instructions and the register(s) involved in each data hazard. The given sequence of instructions cannot execute correctly on the datapath under consideration. However, it is possible to achieve correct execution, even without any forwarding, by keeping the instructions in the given order and insetting nop instructions at appropriate places. Of course. that will increase the execution time, but an incorrect result is unacceptable, however quickly it is computed. Rewrite the given sequence of instructions, adding the minimal nop instructions necessary to achieve correct execution as efficiently as possible. It is sometimes possible to reorder a sequence of instructions to eliminate some or all data hazards, while still achieving the correct result (i.e.. at the end. we have the same values in all registers as before the reordering was applied). Rewrite the given sequence of instructions, using reordering and inserting nop instructions as necessary. to achieve the correct result as efficiently as possible.
Explanation / Answer
for ques.. 7) please refer the following source
http://academic.csuohio.edu/yuc/comp-org/4th-ch4-6.pdf
