Consider a processor with a delayed branch that has three delay slots. Three com

Question

Consider a processor with a delayed branch that has three delay slots. Three compilers compiler A, compiler B and

compiler C, could run on this processor. Compiler A can fill the first delay slot 60% of the time and the second

delay slot 40% of the time and the third delay slot 20% of the time (filling delay slot is independent). Compiler B

can fully fill all the three delay slots. Compiler C leaves all the slots empty. Assuming that branches account for

20% of all instructions and arithmetic/logic operations for the remaining 80% of the instructions for any program,

what is the improvement of CPI with compiler B compared to CPI with compiler A and compared to CPI with

compiler C? Assume that CPI of arithmetic/logic operations is 1.

Explanation / Answer

Compiler B=(1-(1/48000))*20/100

Compiler C=((0.1999+109/120))-1

                  0.3082=30.82%

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