Ok first off this is an entry level VHDL course so no complex operators are expe

Question

Ok first off this is an entry level VHDL course so no complex operators are expected to be used. The assignment is to take two 4 bit signed vector inputs and return an 8 bit vecor output based on a 3 bit selector input. Im having an issue getting the mathematical operations to work that involve signed binary numbers on a simple binary ALU program.

My professor mentioned that all you need to do to get the proper results is concatenate a '1111' to the front of the input if the first bit is a '1' and '0000' if it is not. I have implemented this and the results are even worse. everything works so far except for addition, subtraction, and multiplication. Ill paste the program i have so far under this. Thanks in advance for any help.

use IEEE.STD_ LOGIC_ SIGNED.ALL ENTITY lab 5 IS PORT(A, B IN STD_LOGIC_VECTOR(3 DOWNTO 0) S IN STD_LOGIC_VECTOR(2 DOWNTO 0) Z: OUT STD_LOGIC R: OUT STD LOGIC_VECTOR(7 DOWNTO 0)) END lab-5; ARCHITECTURE behavioral OF lab 5iS SIGNAL Auns, Asig, Buns, Bsig, reg, tempReg STD_LOGIC_VECTOR(7 DOWNTO 0), SIGNAL Acon, Bcon : STD_LOGIC_VECTOR(3 DOWNTO 0) BEGIN AsigAcon & A; BsigBcon & B; Auns"0000" & A; Buns ,'0000" & Bi Rreg; PROCESS (S, Asig, Bsig, Acon, Auns, Buns, Bcon, tempReg, A, B) BEGIN IF (A regAuns XOR Buns, WHEN "011 regNOT Auns, WHEN "100> RegAsig + Bsig; WHEN 101 regAsig-Bsigi WHEN "110"-> reg = A * B; WHEN 111> reg(NOT Asig) + 1; WHEN OTHERS => reg"00000000", END CASE IF (reg - "00000000") THEN ELSE END IF END PROCESS; END behavioral;

Explanation / Answer

operations can't be performed on signals

so you need to define in terms of input nad output( Auns and Buns for your program)

corrected code

WHEN"100"=>

reg=>Auns+Buns;

WHEN"101"=>

reg=>Auns-Buns;

WHEN"110"=>

reg=>Auns*Buns;

do the necessary correction it will work fine.

or u should simply try by

WHEN"100"=>

reg=>A+B;

WHEN"101"=>

reg=>A-B;

WHEN"110"=>

reg=>A*B;

it will work fine as i think

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