Consider a hypothetical 32 bit microprocessor having 32 bit instructions compose

Question

Consider a hypothetical 32 bit microprocessor having 32 bit instructions composed of two fields: The first 4 bits contains the opcode and the remainder an immediate operand, an operand address, or register references. a. What is the maximum directly addressable in bytes. b. What is the impact on system speed if the microprocessor bus has: 1. a 32 bit local address bus and a 16 bit local data bus 2. a 16 bit local address bus and a 16 bit local data bus c. Is this machine more likely to be a RISC or CISC architecture? Why?

Explanation / Answer

a.      2^28 = 256 Mbytes

   b. (1) If the local address bus is 32 bits, the whole address can be transferred at once and decoded in memory. However, since the data bus is only 16 bits, it will require 2 cycles to fetch a 32-bit instruction or operand.

(2) The 16 bits of the address placed on the address bus can't access the whole memory. Thus a more complex memory interface control is needed to latch the first part of the address and then the second part (since the microprocessor will end in two steps). For a 32-bit address, one may assume the first half will decode to access a "row" in memory, while the second half is sent later to access a "column" in memory. In addition to the two-step address operation, the microprocessor will need 2 cycles to fetch the 32 bit instruction/operand.

c.         A RISC architecture. There are only 24 = 16 different opcodes.

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