Digital Integrated Circuits PMOS The following figure shows a circuit that uses

Question

Digital Integrated Circuits PMOS

The following figure shows a circuit that uses a PMOS device to discharge a capacitor. The input Vin switches from 2.5V to ov at time 0. The output voltage of the capacitor (i.e. Vo) is initialized to 2.5V. For simplicity, ignore the body effect. What is the lowest voltage that Vo can reach at the end of the discharging process? How many different operation modes does the PMOS go through during this discharging process? Repeat the above two questions by replacing the transistor with an NMOS and switch the input Vin from 0V to 2.5V. HA in

Explanation / Answer

ANSWER:

a) The PMOS will be switched ON only when |Vgs| > |Vtp|. Since the voltage at the source of the PMOS keeps on changing, it would come down only till Vg + |Vtp| = |Vtp| since Vg is 0V.

Hence the lowest voltage to which Vo can go is |Vtp|.

b) Initially at time t<0, |Vgd| = 2.5 - 0 = 2.5 > |Vtp|. Hence initially the PMOS is in linear region. At t=0 and during the discharge, |Vgd| = 0-0 = 0 < |Vtp|. Hence it is in saturation for time t>=0. Later after discharging,the PMOS is switched off since |Vgs| < |Vtp|.

Hence intially, the PMOS is in linear region, then it comes to saturation region and finally gets switched off.

c) The NMOS will be switched ON only when Vgs > Vtn. Since the voltage at the source of the NMOS is fixed at 0V, and the gate is at 2.5V, it would never be switched off.

Even when the drain voltage of the NMOS is changing, it would never get switched off. Hence the least voltage Vo can go is 0V.

Initially for time t<0, Vgs=0. Hence it is switched off initially. At t=0 and during the discharge, Vgd changes from 0 to 2.5V. Hence it is in saturation for time t=0 and comes to linear region while discharging. Hence intially, the NMOS is swotched off, then it comes to saturation region and finally into the linear region.

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