Consider a computer system with the following specification: The processor uses

Question

Consider a computer system with the following specification: The processor uses a 5-stage MIPS pipe, running at 500 MHz. The I-cache miss ratio is 2%. The miss ratio of the D cache is 10%. There is a 30% chance for an instruction to access a D-cache. Each cache has a cache block size of 4 words. The memory is interleaved with 4 memory banks. The memory bus clock is 100 MHz and the bus is one word wide. To access the memory, it takes one bus clock cycle to send the address, 5 bus clock cycles for each memory access initiated (DRAM latency), and one bus clock cycle to send a word of data. Assume the CPI (cycle per instruction) for the processor is 1.4 when no cache miss is considered. How many CPU clock cycles does it take to fill an I-cache block (when a miss occurs)? What is the CPI, in terms of the CPU clock cycles, when (only) I-cache misses are considered? What is the CPI, in terms of the CPU clock cycles, when all cache misses are considered? How much execution time in seconds does it take to execute ten billion instructions?

Explanation / Answer

Given pipelining, out of order processing, microcode, multi-core processors, etc there is no guarantee that a particular section of assembly code will take exactly x CPU cycles/clock cycle/whatever cycles.

If such a reference exists, it will only be able to provide broad generalizations given a particular architecture, and depending on how the microcode is implemented you may find that the Pentium M is different than the Core 2 Duo which is different than the AMD dual core, etc.

Note that this article was updated in 2000, and written earlier. Even the Pentium 4 is hard to pin down regarding instruction timing - PIII, PII, and the original pentium were easier, and the texts referenced were probably based on those earlier processors that had a more well-defined instruction timing.

These days people generally use statistical analysis for code timing estimation.

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