· Question 1 2 out of 5 points For a direct-mapped cache design with a 64-bit ad
ID: 3577222 • Letter: #
Question
· Question 1
2 out of 5 points
For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache.
Tag
Index
Offset
63-10
9-5
4-0
Beginning from power on, the following references (addresses in decimal) are recorded:
0
4
16
132
232
160
1024
30
140
3100
180
2180
What is the hit ratio? Enter your answer in decimal reounded to 2 decimal places
· Question 2
2 out of 5 points
Consider an implementation of an instruction set architecture. The instructions can be divided into four classes according to their CPI classes (classes A, B, C, and D). The processor has a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3.
Given a program with a dynamic instruction count of 2.0 E6 (meaning 1.0*10^6) instructions divided into classes as:
10% class A
20% class B
50% class C
20% class D
Find the number of clock cycles required in mega. if you answer is 3.3 * 10^6, then enter 3.3
· Question 3
5 out of 5 points
What is the R-type mips instruction corresponding to:
0x 012A5822
Use register number, not register name when submitting your answer.
For 0x 001580C0 the answer to submit would be ssl $16, $21, 3; NOT ssl $s0, $s5, 3
· Question 4
5 out of 5 points
The amount of hardware decreases with parallel processing
· Question 5
2 out of 5 points
For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache.
Tag
Index
Offset
63-10
9-5
4-0
How many blocks does the cache have? Only enter the numeric value
· Question 6
5 out of 5 points
An interrupt is an external event which requires attention by a program. There are two types of interrupts: hardware interrupts and software interupts.
· Question 7
2 out of 5 points
For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache.
Tag
Index
Offset
63-10
9-5
4-0
What is the cache block size (in words)? In other words, how many words per block for this configuration? Only enter the numeric value
· Question 8
2 out of 5 points
Assume the following register contents:
$10 = 0x0000000A
$11 = 0x12345678
what is the value of register $12 after the folowing sequence of instruction?
sll $12, $10, 4
or $12, $12, $11
Enter your answer in hexadecimal (starting with 0x), no space, use cap for letter. example 0x2016B777
· Question 9
2 out of 5 points
Assume that for a given program the instructions are distributed in these categories:
70% are arithmetic
10% are load/store
20% are branch
Given this instruction mix and the assumption that:
an arithmetic instruction requires 2 cycles
a load/store instruction takes 6 cycles
a branch instruction takes 3 cycles
For a 25% improvement in performance (here the CPI), what is the new average CPI. Round your answer to 2 decimal places.
· Question 10
2 out of 5 points
Which of these instructions use sign extend?
· Question 11
2 out of 5 points
Assume a 18 cm diameter wafer has a cost of 12, contains 84 dies, and has 0.020 defects/squared-cm.
If the number of dies per wafer increased by 12% and the defects per area unit increased by 15%, find the yield.
Only enter numeric value rounded to 4 decimal places
· Question 12
5 out of 5 points
Consider an implementation of an instruction set architecture. The instructions can be divided into four classes according to their CPI classes (classes A, B, C, and D). The processor has a clock rate of 3.0 GHz and CPIs of 1, 2, 3, and 4.
Given a program with a dynamic instruction count of 1.0 E6 (meaning 1.0*10^6) instructions divided into classes as:
10% class A
20% class B
50% class C
20% class D
Find the global CPI, enter numeric value rounded to 2 decimal places.
· Question 13
5 out of 5 points
An arithmetic left shift multiplies a signed binary number by 2.
· Question 14
5 out of 5 points
Assume that individual stages of the datapath have the following latencies:
IF
ID
EX
MEM
WB
250ps
350ps
150ps
300ps
200ps
What is the total latency of a load in non pipelined processor? Only enter the number, not ps
· Question 15
5 out of 5 points
Assume 185 and 122 are unsigned 8-bit decimal integers. Calculate 185 - 122. Is there overflow, underflow, neither, both?
· Question 16
2 out of 5 points
Consider the following code:
addi $t1, $t2, 3
add $t3, $t1, $t2
addi $t4, $t1, 7
add $t5, $t3, $t2
How many NOPs (bubbles) are needed so that this code will run correctly on a pipeline that does not handle data hazards? submit the minimum number of NOPs needed.
· Question 17
5 out of 5 points
Assume that individual stages of the datapath have the following latencies:
IF
ID
EX
MEM
WB
250ps
350ps
150ps
300ps
200ps
What is the clock cycle time in a non-pipelined processor in ps? Only enter the number, not ps
· Question 18
5 out of 5 points
Associative memeories are used in applications where the searching is time critical and search time has to be very short.
· Question 19
5 out of 5 points
Assume that individual stages of the datapath have the following latencies:
IF
ID
EX
MEM
WB
250ps
350ps
150ps
300ps
200ps
What is the clock cycle time in a pipelined processor in ps? Only enter the number, not ps
· Question 20
2 out of 5 points
For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache.
Tag
Index
Offset
63-10
9-5
4-0
What is the ratio between total bits required for such a cache implementation over the data storage bits?
Wednesday, November 30, 2016 7:55:24 PM EST
For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache.
Tag
Index
Offset
63-10
9-5
4-0
Beginning from power on, the following references (addresses in decimal) are recorded:
0
4
16
132
232
160
1024
30
140
3100
180
2180
What is the hit ratio? Enter your answer in decimal reounded to 2 decimal places
Explanation / Answer
Answer 5
Number of cache block = 2^index bits which means 2^5 hence it will have 5 cache blocks.
Answer 7
Cache block size = 2^offset bits which is 2^5 bytes or we can say 2^3 words which is 8 words.
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