20. Which of the following interrupts cannot be ignored by the CPU? A. Timer B.
ID: 3602249 • Letter: 2
Question
20. Which of the following interrupts cannot be ignored by the CPU? A. Timer B. Serial C. Reset D. Serial communication 21. A subroutine called from within another subroutine is referred to as a_ A. caged subroutine B. secondary subroutine C. stacked subroutine D. nested subroutine 22. Executing the instruction MOV P1, A cause's A. the data in A to be sent out port P1 for a brief timer interva B. the value contained in A to be sent out port P1 and latched C. register A to be set to the value contained in port P1 D. the value in port P1 to be set to the constant A 23. What is the final result in the accumulator after the execution of the following program segment? MOV A, #55H ANL A, #0FH CPLA A. 55H B. FAH C. AAH D. 35H 24. Which of the following is always bi-directional? A. The enable line B. The address bus C. The data bus D. The control busExplanation / Answer
[20] [D]
Reason : Non-Maskable Interrupts There are some interrupts which cannot be masked out or ignored by the processor. These are associated with high priority tasks which cannot be ignored (like memory parity or bus faults). In general, most processors support the Non-Maskable Interrupt (NMI). This interrupt has absolute priority, and when it occurs, the processor will finish the current memory cycle, then branch to a special routine written to handle the interrupt request.
[21] [D]
Nesting – One subroutine calls another
[22] [B]
MOV P1,A ;send it to port 1
[23] [C]
Operation: ANL
Function: Bitwise AND
Operation: CPL
Function: Complement Register
. If operand is the Accumulator then all the bits in the Accumulator will be reversed
MOV --> 55H 01010101
ANL --> 0FH 00001111
-----------------------------
00000101
Reverse : 11111010 [FAH]
[24] [C]
Reason : data bus is bidirectional because it transfers information between peripheral devices and memory register.but,address bus is unidirectional because it simply recieves information
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