Examine each of the following instructions. Assume that each instruction is inde

Question

Examine each of the following instructions. Assume that each instruction is independent and resets with the initial condition before the next instruction. For each instruction show the entire 32-bit contents of each destination register. Show your work in the Work column if needed (to get partial credits) Register File Memory Contents Sto-Ox0000743C St1= | 0x00007448 St20x000000B1 St30x00000006 St40xFFFFFFF8 $t50x00000000 St60x000080AC 0x74500xBCDEF012 0x744c0x9A785630 0x74480xEF05C738 0x74440x95DE50FO 0x74400x23456789 0x743c0xCDEF0123 0x74380x89AB1234 Instruction lb $t5,-15 ($tl) lhu $t5, Oxfff0 ($tl) lw $t5, 0x14 ($t0) srl $t5, $t4,!5 lui $t5, 0x12.3 andi $t5, $t4,7 xor $t5, $t2, $t3 slt $t5, $t4,$t1 Result Work $t5 = $t5 =

Explanation / Answer

1)
lb $t5,-15($t1)

=> $t5 = 0x12

Working :- $t5 = data in address [$t1 - 15] = data in address 0x7439 = 0x12

2)
lhu $t5,0xfff0($t1)

Working :- $t5 = <- zero-extended halfword from address $t1 + 0xfff0 <- 0x7438

=> $t5 = 0x00001234

3)
lw $t5,0x14($t0)

Working :- $t5 = <- word from address $t0+0x14 = <- 0x7450

=> $t5 = 0xBCDEF012

4)srl $t5,$t4,5

working:- $t5 = $t4 >> 5 = 0xFFFFFFF8 >> 5

=> $t5 = 0x07FFFFFF

5)
lui $t5,0x123

working :- $t5 = (0x123) << 16

$t5 = 0x01230000

6)
andi $t5,$t4,7

working :- $t5 = $t4 & 7 => 0xFFFFFFF8 & 7

$t5 = 0x0

7) xor $t5,$t2,$t3

working :- $t5 = $t2 xor $t3 => 0x000000B1 xor 0x00000006 =>

$t5 = 0x000000B7

8)
slt $t5,$t4,$t1

working :- $t5 will set if $t4 < $t1 => 0xFFFFFFF8 < 0x00007448

$t5 = 0

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