This subject is computer Architecture organization Draw a flowchart showing the

Question

This subject is computer Architecture organization

Draw a flowchart showing the steps for a CPU program that uses programmed I/O to send a string consisting of 10 characters to a printer connected through a UART interface. Assume that the string is stored in memory starting at address 100. Consider the following while developing your flowchart:

Assume that the interface has already been initialized to work in the right mode of operation

Show each memory or I/O read or write operation as an explicit step in your flowchart

Assume that the CPU has multiple data registers R1, R2, … etc. If you need variables for your algorithm (e.g. for counters or addresses), you can use a register to store and maintain such variables.

Explanation / Answer

| P a g eCompiled By:- Deepak Kumar KarnChapter 1 :- Introduction1.) Expanded Structure of IAS computer:-Figure :- Expanded structure of IAS computerMemory buffer register (MBR):-Contains a word to be stored in memory or sent to the I/O unit, or is usedto receive a word from memory or from the I/O unit.Memory address register (MAR) :- 5. 2 | P a g eCompiled By:- Deepak Kumar KarnSpecifies the address of memory in the word to be written from or readinto the MBR.Instruction register (IR) :-Contains the 8 bits Opcode instruction being executed.Instruction buffer register (IBR):-Employed to hold temporarily the right- hand instruction from a wordin memory.Program counter (PC):-Contains the address of the next instruction-pair to be fetched frommemory.Accumulator (AC) and multiplier quotient (MQ):-Employed to hold temporarily operands and results of ALU operations.For example, the result of multiplying two 40-bit numbers is an 80-bitnumber; the most significant 40 bits are stored in the AC and the leastsignificant in the MQ.Central processing unit (CPU):-Controls the operation of the computer and performs its data processingfunctions; often simply referred to as processor.I/O:-Moves data between the computer and its external environment. 6. 3 | P a g eCompiled By:- Deepak Kumar Karn2.) Flow chart of IAS Computer:- 7. 4 | P a g eCompiled By:- Deepak Kumar KarnThe IAs operates by respectively performing as instruction cycle. Eachinstruction cycle consists of two sub-cycles.Fetch Cycle:-The opcode of next instruction is loaded into the IR and the addressportion is loaded into the MAR. This instruction may be taken from the IBR,or it can be obtained from memory by loading a word into the MBR, andthen down to the IBR, IR and MAR.Execute Cycle:-The control circuitry interprets the Opcode & executes the instruction bysending out the appropriate control signals to cause data to be moved oran operation to be performed by the ALU.3.)IAS instruction format:-The memory of IAS consists of 1000 storage locations called words of 40binary digits each. Both data & instructin are stored there, Number arerepresented in binary form.Fig. IAS Format 8. 5 | P a g eCompiled By:- Deepak Kumar KarnEach number is represented by a sign bit and a 39 bit value. A word mayalso contain 20 bit instruction consisting of an 8 bit operation code(opcode)specifying the operation to be performed and 12 bit address designing oneof the words in memory (numbered from 0 to 999)IAS computer had a total of 21 instruction that can be grouped as follows.1. Data transfer:-Move data between memory and ALU register or between two ALUregisters.2. Unconditional branch:-The control unit executes instruction in sequence from memory.There sequence can be changed by a branch instruction which facilitatesrepetitive operations.3. Conditional branch:-Branch can be made dependent on a condition thus allowing decisionpart.4. Arithmetic:-It comprises operation performed by ALU5. Address modify:-It permits address to be computed in ALU and then inserted intoinstruction stored in memory.4.) The difference between computer Organization and ComputerArchitecture:- 9. 6 | P a g eCompiled By:- Deepak Kumar KarnComputer organizationDeals with all physical components of computer systems thatinteracts with each other to perform various functionalitiesThe lower level of computer organization is known as micro-architecture which is more detailed and concrete.Examples of Organizational attributes includes Hardware detailstransparent to the programmer such as control signal and peripheral.Computer architectureRefers as a set of attributes of a system as seen by programmerExamples of the Architectural attributes include the instruction set,the no of bits used to represent the data types, Input Outputmechanism and technique for addressing memories.The difference between architecture and organization is best described bya non-computer example. Is the gear level in a motorcycle part of it isarchitecture or organization? The architecture of a motorcycle is simple; ittransports you from A to B. The gear level belongs to the motorcyclesorganization because it implements the function of a motorcycle but is notpart of that function5.)Scale Of Integration:-The number of components fitted into a standard size IC represents itsintegration scale, in other words it’s a density of components. It is classifiedas follows:SSI – Small Scale IntegrationIt have less than 100 components (about 10 gates).MSI – Medium Scale IntegrationIt contains less than 500 components or have more than 10 but less than100 gates. 10. 7 | P a g eCompiled By:- Deepak Kumar KarnLSI – Large Scale IntegrationHere number of components is between 500 and 300000 or have morethan 100 gates.VLSI – Very Large Scale IntegrationIt contains more than 300000 components per chipVVLSI - Very Very Large Scale IntegrationIt contains more than 1500000 components per chip. 11. 8 | P a g eCompiled By:- Deepak Kumar Karn 12. 9 | P a g eCompiled By:- Deepak Kumar KarnChapter2:- Central Processing Unit1.) ALU:-The ALU is the part of computer that actually performs arithmetic & logicaloperations. All of other elements in the computer system, control unit,register, memory, I/O are there mainly to bring data into ALU for it toprocess and then to take results back.2.)Sign-magnitude representation:-The most significant(left side) bit in the word as a sign bit.Sign bit 0 +Ve number1 -ve numberEg.+18 00010010-18 10010010Drawbacks:Addition and subtraction require a consideration of both the sign ofthe numbers and their magnitude to carry out the required operation. 13. 10 | P a g eCompiled By:- Deepak Kumar Karn+0 = 0000 0000-0= 1000 0000This is inconvenient because it is slightly more difficult to test for 0, (whichappears frequently on computers)3.) Two’s complement representation:-Like sign magnitude, two’s complement representation uses themost significant bit as a sign bit, making it easy to test whether it is +ve or –ve.-7 = 1 1 1 1Sign MagnitudeAnd its 2’s complement is=10015= 0 1 0 1And its 2’s complement is=0101Addition:--7 = 1 0 0 1 -4 = 1 1 0 0+ 5 = 0 1 0 1 + 4 = 0 1 0 0-2 = 1 1 1 0 -0= 1 0 0 0 0The result may be larger that can be held in the word size being used.This condition is overflow.1 14. 11 | P a g eCompiled By:- Deepak Kumar KarnOverflow rule:- If two number are added, and they are both positive ornegative than overflow occurs if and only if the result has opposite sign.5 = 0 1 0 14 = 0 1 0 01 0 0 1` -7 = 1 0 0 1 Over flow-6 = 1 0 1 01 0 0 1 1Subtraction:-To subtract one number (subtrahend) from another number(minuend), take the 2’s complement (negative) of the subtrahend and addit to the minuend.M=2 s= 7-7 = 2’s complement of 0111= 1000+ 11001Therefore, 2-7 = 2+ (-7)001010011011 15. 12 | P a g eCompiled By:- Deepak Kumar KarnBlock Diagram of H/W Addition Subtraction:Q. Explain the algorithm for signed magnitude numberaddition/subtraction with suitable examples.Ans.:-M(mode control)AVfo/p CarryLoad SumFig: Hardware for signed magnitude addition & subtraction.BSEASB-RegisterComplementParallel AdderA-register 16. 13 | P a g eCompiled By:- Deepak Kumar KarnAbove block diagram for addition and subtraction consist of register A&Band sign flip-flop AS & BS subtraction is done by adding A to the 2’scomplement of B.The o/p carry is transfer flip-flop E where it can be checked to determinethe relative magnitude of two magnitude.The add overflow flip-flop(AOF) holds the overflow when A & B areadded.The A register provides other micro operation that may be needed whenwe specify sequence of steps.The addition of A+B is done through the parallel adder.The complement provides the o/p of B or the complement of Bdepending on the state of mode control M. The M signal also applied to thei/p carry of the adder when M=0, the value of B is transfer to the adder, thei/p carry is zero & the o/p of the adder is equal to sum A+B.When M=1, the one’s complement of B is applied to the adder, the i/pcarry is I & O/P = A+B+I which is equal to A+2’s complement of B. Againwhich is equivalent to the subtraction A-B.Multiplication: 17. 14 | P a g eCompiled By:- Deepak Kumar KarnExample1:- Multiplication Of Unsigned Binary Integers(1011) (1101) = (10001111)(11*13) = (143)Block Diagram of multiplication:-(b) Above Example 1Fig. Hardware Implementation of Unsigned Binary Multiplication 18. 15 | P a g eCompiled By:- Deepak Kumar KarnAnother Example of Multiplication:-1010*1100C A Q M0 0000 1010 1100Since,Q0=0 0 0000 0101 1100 1stCycleSince,Q0=1 C,A A+M0 1100 0101 1100—add0 0110 0010 1100—shift 2ndCycleSince,Q0=00 0011 0001 1100—shift 3rdCycleSince,Q0=1 C,AA+M0 1111 0001 1100—add 4thCycle0 0111 1000 1100—shiftAnswer = 0111 1000 19. 16 | P a g eCompiled By:- Deepak Kumar KarnFlowchart of Multiplication:-Fig. Flow chart of unsigned binary multiplication 20. 17 | P a g eCompiled By:- Deepak Kumar Karn#. Two’s complement Multiplication Booth’s Algorithm:-Fig. Booth’s Algorithm for twos Complement Multiplication 21. 18 | P a g eCompiled By:- Deepak Kumar KarnExample:Booth’s Algorithm (7*3)Since, Q =11Since, Q =01Since, Q =00AQ= 0001 0101Answer 22. 19 | P a g eCompiled By:- Deepak Kumar KarnAnother Example:-7*3A Q M000 0011 0 1001Q =10 A A-M0111 0011 0 1001 AA-M0011 1001 1 1001 ShiftQ = 110001 1100 1 1001 ShiftQ =01 AA+M1010 1100 1 10011101 0110 0 1001Q =001110 1011 0 1001Note:In either of the case, the right shift is such that the leftmost bit of Anamely , not only is shifted into but also remains in . This isrequired to preserve the sign of the number in A&Q. It is known asarithmetic shift it preserves sign bit. 23. 20 | P a g eCompiled By:- Deepak Kumar KarnDivision: Division of unsigned binary division.Flowchart of unsigned Binary division.Fig. FLOWCHART UNSIGNED BINARY DIVISION

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