In this exercise we examine how the clock cycle time of the processor affects th

Question

In this exercise we examine how the clock cycle time of the processor affects the design of the control unit, and vice versa. Problems in this exercise assume that the logic blocks used to implement the datapath have the following latencies: To avoid lengthening the critical path of the datapain shown in Figure 4.24, how much time can the control unit take to generate.the MemWrite signal. Which control signal in Figure 4.24 has the most slack how much time does the control unit have to generate it if it wants to avoid being on the critical path? Which control signal in Figure 4.24 is the most critical generate quickly and how much time does the control unit have to generate it if it wants to avoid being on the critical path?

Explanation / Answer

please rate - thanks 4.10.1 The Control unit can begin generating MemWrite only afterI-Mem is read. It must finish generating this signal before the endof the clock cycle. MemWrite is a write-enable signal forD-Mem flip-fl ops, and the actual write is triggered by the edge ofthe clock signal, so MemWrite doesn't need to arrive before thattime. the Control unit must generate the MemWrite in one clockcycle, minus the I-Mem access time: a.)Critical path 400ps + 30ps + 200ps + 30ps +120ps + 350ps +30ps = 1160ps Maximum time to generate MemWrite 1160ps – 400ps= 760ps b). Critical path 500ps + 100ps + 220ps + 100ps +180ps + 1000ps +100ps = 2200ps Maximum time to generate MemWrite 2200ps – 500ps = 1700ps 4.10.2 All control signals start to be generated after I-Mem readis done. The most slack a signal can have is until the end of thecycle, and MemWrite and Reg- Write are both needed only at the endof the cycle, so they have the most slack. The time to generate both signals without increasing the criticalpath is the one computed in 4.10.1. 4.10.3 MemWrite and RegWrite are only needed by the end of thecycle. RegDst, Jump, and MemtoReg are needed one Mux latency beforethe end of the cycle, so they are more critical than MemWrite andRegWrite. Branch is needed two Mux latencies before the end of the cycle, so it is morecritical than these. MemRead is needed one D-Mem plus one Muxlatency before the end of the cycle, and D-Mem has more latencythan a Mux, so MemRead is more critical than Branch. ALUOp must get to ALU control in time to allow one ALUCtrl, one ALU, one D-Mem, and one Mux latency before the end of thecycle. This is clearly more critical than MemRead. Finally, ALUSrcmust get to the pre-ALU Mux in time, one Mux, one ALU, one D-Mem,and one Mux latency before the end of the cycle. Again, this ismore critical than MemRead. Between ALUOp and ALUSrc, ALUOp is morecritical than ALUSrc if ALU control has more latency than a Mux. IfALUOp is the most critical, it must be generated one ALU Ctrllatency before the critical-path signals can go through Mux, Regs,and Mux. If the ALUSrc signal is the most critical, it must begenerated while the critical path goes through Mux and Regs. Wehave a. The most critical control signal is ALUOp Time to generateit without affecting the clock cycle time(50ps > 30ps) 30ps +200ps + 30ps – 50ps = 210ps b. The most critical control signal is ALUSrc (100ps > 55ps)Time to generate it without affecting the clock cycle time 100ps +220ps = 320ps

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