Problems in this exercise assume that instructions executed by a pipelined proce

Question

Problems in this exercise assume that instructions executed by a pipelined processor are broken down as follows: Assuming there are no stalls and that 60% of all conditional branches are taken, in what percentage of clock cycles does the branch adder in the EX stage generate a value that is actually used? Assuming there are no stalls, how often (percentage of all cycles) do we actually need to use all three register ports (two reads and a write) in the same cycle? Assuming there are no stalls, how often (percentage of all cycles) do we use the data memory?

Explanation / Answer

please rate - thanks 4.17.1 the value produced by this adder is actuallyused by a beq instruction when the branch is taken. a) (60% of 25%)=15% b) (60% of 15%)=9% 4.17.2 only add needs all three register ports (reads two and writeone). beq and sw does not write any register, and lw only uses oneregister value. a) 50% b) 30% 4.17.3 lw and sw use the data memory. a. 25% (15% + 10%) b. 55% (35% + 20%)

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