Consider a branch-target buffer that has penalties of 0, 2, and 2clock cycles fo

Question

Consider a branch-target buffer that has penalties of 0, 2, and 2clock cycles for correct conditional branch prediction, incorrectprediction, and a buffer miss, respectively. Consider abranch-target buffer design that distinguishes conditional andunconditional branches, storing the target address for aconditional branch and
the target instruction for an unconditional branch.
a. What is the penalty in clock cycles when an unconditional branchis found in the buffer?
b. Determine the improvement from branch folding for unconditionalbranches. Assume a 90% hit rate, an unconditional branch frequencyof 5%, and a 2-cycle penalty for a buffer miss. How muchimprovement is gained by this enhancement?

I am pretty sure part a is 0 because it is the same as an correctlypredicted branch. not sure about part b.

thanks.

Explanation / Answer

can you elaborate a little more about part B. i understand partA. I am not sure how it pertains to branch folding. thanks. would the speedup for your solution would be .01/.035 = .29 ?

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