Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an

Question

Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input close cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain in bytes/s? To Increase is performance, would it be better to make its external bus 32 bits or to double the external clock frequency? Hint: Determine the number of bytes that can be transferred per bus cycle

Explanation / Answer

Remember the reciprocal relationship between frequency and period. Also it takes one bus cycle to transfer 2 bytes. How long is a bus cycle? See “tips log” for more tips.


Clock cycle = 1/(8 MHz) = 0.125*10-6 = 125 ns
Bus cycle = 4 * 125 ns = 500 ns

2 bytes transferred every 500 ns; thus transfer rate = 2/500ns = 4 MBytes/sec, where Mega is 106 in this case.

Doubling the frequency may mean adopting a new chip manufacturing technology (assuming each instructions will have the same number of clock cycles); doubling the external data bus means wider (maybe newer) on-chip data bus drivers/latches and modifications to the bus control logic. In the first case, the speed of the memory chips will also need to double (roughly) not to slow down the microprocessor; in the second case, the "word length" of the memory will have to double to be able to send/receive 32-bit quantities.

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