I am asked to create an ALU that accepts two 4-bit inputs (A0-A3, B0-B3), a 3-bi
ID: 3645446 • Letter: I
Question
I am asked to create an ALU that accepts two 4-bit inputs (A0-A3, B0-B3), a 3-bit function selection code (F0-F2) and outputs a 5-bit result (S0-S4). Here is the code I have so far, if anyone can help with the proper coding, I would appreciate it, as I continue to have errors during compile.LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY alu4bit IS
PORT( a, b, : IN integer RANGE 0 TO 15;
F : IN integer RANGE 0 TO 7;
S : OUT integer RANGE 0 TO 31);
END alu4bit;
ARCHITECTURE arc OF alu4bit IS
BEGIN
PROCESS(a, b, F)
BEGIN
IF (f = "000") THEN S<= a;
ELSIF (f = "001") THEN S<= NOT a;
ELSIF (f = "010") THEN S<= a + b;
ELSIF (f = "011") THEN S<= a - b;
ELSIF (f = "100") THEN S<= b;
ELSIF (f = "101") THEN S<= NOT b;
ELSIF (f = "110") THEN S<= a + 1;
ELSIF (f = "111") THEN S<= a - 1;
END IF;
END PROCESS;
END arc;
Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_VHDL is
port
(
Nibble1, Nibble2 : in std_logic_vector(3 downto 0);
Operation : in std_logic_vector(2 downto 0);
Carry_Out : out std_logic;
Flag : out std_logic;
Result : out std_logic_vector(3 downto 0)
);
end entity ALU_VHDL;
architecture Behavioral of ALU_VHDL is
signal Temp: std_logic_vector(4 downto 0);
begin
process(Nibble1, Nibble2, Operation, temp) is
begin
Flag <= '0';
case Operation is
when "000" => -- res = nib1 + nib2, flag = carry = overflow
Temp <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(Nibble2)));
Result <= temp(3 downto 0);
Flag <= temp(4);
when "001" => -- res = |nib1 - nib2|, flag = 1 iff nib2 > nib1
if (Nibble1 >= Nibble2) then
Result <= std_logic_vector(unsigned(Nibble1) - unsigned(Nibble2));
Flag <= '0';
else
Result <= std_logic_vector(unsigned(Nibble2) - unsigned(Nibble1));
Flag <= '1';
end if;
when "010" =>
Result <= Nibble1 and Nibble2;
when "011" =>
Result <= Nibble1 or Nibble2;
when "100" =>
Result <= Nibble1 xor Nibble2;
when "101" =>
Result <= not Nibble1;
when "110" =>
Result <= not Nibble2;
when others => -- res = nib1 + nib2 + 1, flag = 0
Temp <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(not Nibble2)) + 1);
Result <= temp(3 downto 0);
Flag <= temp(4);
end case;
end process;
end architecture Behavioral;
Basically you are not taking proper case of letters library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_VHDL is
port
(
Nibble1, Nibble2 : in std_logic_vector(3 downto 0);
Operation : in std_logic_vector(2 downto 0);
Carry_Out : out std_logic;
Flag : out std_logic;
Result : out std_logic_vector(3 downto 0)
);
end entity ALU_VHDL;
architecture Behavioral of ALU_VHDL is
signal Temp: std_logic_vector(4 downto 0);
begin
process(Nibble1, Nibble2, Operation, temp) is
begin
Flag <= '0';
case Operation is
when "000" => -- res = nib1 + nib2, flag = carry = overflow
Temp <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(Nibble2)));
Result <= temp(3 downto 0);
Flag <= temp(4);
when "001" => -- res = |nib1 - nib2|, flag = 1 iff nib2 > nib1
if (Nibble1 >= Nibble2) then
Result <= std_logic_vector(unsigned(Nibble1) - unsigned(Nibble2));
Flag <= '0';
else
Result <= std_logic_vector(unsigned(Nibble2) - unsigned(Nibble1));
Flag <= '1';
end if;
when "010" =>
Result <= Nibble1 and Nibble2;
when "011" =>
Result <= Nibble1 or Nibble2;
when "100" =>
Result <= Nibble1 xor Nibble2;
when "101" =>
Result <= not Nibble1;
when "110" =>
Result <= not Nibble2;
when others => -- res = nib1 + nib2 + 1, flag = 0
Temp <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(not Nibble2)) + 1);
Result <= temp(3 downto 0);
Flag <= temp(4);
end case;
end process;
end architecture Behavioral;
Basically you are not taking proper case of letters Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.