Determine the output of each of the following circuits, assuming that the upper

Question

Determine the output of each of the following circuits, assuming that the upper input is 1 and the lower input is 0. use this device as an abstract tool in other circuits. Consider the circuitry using two of the following flip-flops. If a pulse were sent on the circuit's input, the bottom flip-flop would change state. However, the second flip-flop would not change, since its input (received from the output of the NOT gate) went from a 1 to a 0. As a result, this circuit would now produce the outputs 0 and 1. Determine the output of each of the following circuits, assuming that the upper input is 1 and the lower input is 0. What would be the output when upper input is 0 and the lower input is 1? A second pulse would flip the state of both flip-flops, producing an output of 1 and 0. What would be the output after a third pulse? After a fourth pulse? What Boolean operation docs the circuit compute? If we were to purchase a flip-flop circuit from an electronic component store, we may find that it has an additional input called flip. When this input changes from a 0 to 1, the output flips state (if it was 0 it is now 1 and vice versa). However, when the flip input changes from 1 to a 0, nothing happens. Even though we may not know the details of the circuitry needed to accomplish this behavior, we could still . It is often necessary to coordinate activities of various components within a computer. This is accomplished by connecting a pulsating signal (called a clock) to circuitry similar to part a. Additional gates (as shown) send signals in a coordinated fashion to other connected circuits. On studying this circuit, you should be able to confirm that on the 1st, 5th, 9th ... pulses of the clock, a 1 will be sent on output A. On what pulses of the clock will a 1 be sent on output B? On what pulses of the clock will a 1 be sent on output C? On which output is a 1 sent on the 4th pulse of the clock?

Explanation / Answer

Q1 a. case 1: when uper input is 1 and lower is 0

when we input 1 and 0 lower input becomes 1 and then 1 and 1 will input to XOR gate which will give final output as '0' because if both inputs are same Xor gate will give output 0.

case2: when uper input is 0 and lower is 1.

in this when we input 0 and 1 lower input becomes 0 and then 0 and 0 will input to XOR gate which will give final output as '0' because if both inputs are same Xor gate will give output 0.

Truth Table

input1    input2

0          1

1     

Q1 b: case 1: when uper input is 1 and lower is 0

there are two gates used here first is OR gate and Second is And.

when first 1 and 0 pass to OR gate it gives output as 1 then 1 and 0 pass to And gate which gives final output as 0.

case 12 when uper input is 0 and lower is 1

there are two gates used here first is OR gate and Second is And.

when first 0 and 1 pass to OR gate it gives output as 1 then 1 and 1 pass to And gate which gives final output as 1.

trruth table of AND GAte         

Truth table of OR gate

Q1: c: Here both are XOR gates

Case 1: when we input 1 and 0 then first XOR will give 1 after that 1 and 1 will input to second XOR then final output is 0.

Case2: when we input 0 and 1 then first XOR will give 1 after that 0 and 1 will input to second XOR then final output is 1.

Refer truth table in PartA.

Q2: a: In this we have first 2 not gates then we have one NOR gate

now ((input)'+(input)')'= ((input)')'.((input)')' = ( input.input)-- Answer.

Please note: (input)' means negaton of input.

b: Here NAND gate is used

Please note I am writing INPUT as alphabet I. so where Ever I use alphabet I please consider it as input.

at first Nand gate output will be= (I.I)' after that we have 2 parallel nand gates. SO at first nand gate we have input

I and (I.I)' then output will be (I.(I.I)')'

Similarly at other Nand gate output will be= (I.(I.I)')'

Then these 2 will act as input for final Nand Gate

and output will be--> ((I.(I.I)')'.(I.(I.I)')')'--->   1

you know (A.B)'= A'+B' and (A+B)'=A'.B' so using this

(I.(I.I)')'-->> I+I'

so equation 1 becomes ((I+I').(I+I'))' --> (I+I')'+(I+I')'--> I.I'+I.I'---> 0+0=0 --answer

Q3:a:

In third pulse input changes from 0 to 1 so output of flipflop 1 changes and output of flipflop 2 remains unchange

so final output comes as 1 and 1

In fourth clock pulse again input changes from 1 to 0 so output of flipflop 1 remains unchange and flipflop 2 changes. So output comes as 0 and 1

input1 input2 output 0 1 1 0 0 0 1 0 1

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