We intend to do the address decoding of a system whose microcontroller has 20 ad

Question

We intend to do the address decoding of a system whose microcontroller has 20 address lines (A_0 to A_19) and 8 data lines (D_0 to D_7), that it should access ROM and RAM memories, and interface to an LCD Given the information below: ROM 1 2732. initial address Ok RAM 2 6164. immediately after the ROM LCD uses 4 positions, starting at 60K draw its map memory make its address table relating the address lines to the activation signals the boolean equations for each activation line make a sketch of how the circuit would look like using GATES (no decoder), showing the CPU. peripherals and their address and data buses, and the RD/WR control line from the CPU Note that: the activation lines of the RAM and ROM are active low. for the LCD it is active high the higher address lines that are not mentioned can be presumed as low level all the time. Given the interface circuit between the address lines of a CPU to its peripherals, give the activation signals of each peripheral, indicating if they are active low or high. truth table relating the address lines and the activation signals. draw the memory map indicating the size of the block reserved for each peripheral, indicating the initial and final addresses, both in decimal and hexadecimal. NOTE: The CPU has of 16 address lines and 8 data lines, the memories are 8 bit-wide - careful with the names of the address lines: the MS lines can be assumed low. Explain In your own words the difference between RISC and CISC processors. Explain In your own words how a cache works, and give examples. Explain in your own words what is microprogramming. Give examples of recent processors that have pipeline in their architectures. What are typical improvements seen in processors focused on DSP applications? Give examples of recent processors of at least three different manufacturers.

Explanation / Answer

There are multiple questions in this problem. I will answer few:

3)

Risc stands for reduced instruction set computing and cisc stands for complex instruction set computing. In risc each instruction is meant to do some specific operation and the instruction word is small. In cisc each instruction is meant to do multiple operations wherein with each instruction multiple types of operations are associated.

4)

Cache works by usually providing single cycle accesses for memory and instruction fetches. Caches are usually small in size and they tried to keep the code which in caches from main memory which will be frequently accessed by the processor. With this the code executes faster as the processor first checks in cache and then it goes to main memory. This improves the performance of the cpu.

5)

microprogramming is basically a technique with which we implement hardware logic/control logic which are necessary to execute instruction in a microprocessor.

6)

Usually every procesor is using pipeline as it helps to achieve more throughput. You can take any ARM processor like Corex M3,Cortex M7, Cortex A53 all have pipeline based design in the them.

7)

In DSP processors special hardware is added to support DSP instruction. Usually it's a combination of adder, shifter and a multiplier to process all the DSP instructions. There are multiple processors from Cadence(tensilica) and Synopsys(Arc) in this category.

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