Consider the following loop. loop: lw r1, 0(r1) and r1, r1, r2 lw r1, 0(r1) lw r

Question

Consider the following loop. loop: lw r1, 0(r1) and r1, r1, r2 lw r1, 0(r1) lw r1, 0(r1) beq r1, r0, loop Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, and that the pipeline has full forwarding support. Also assume that many iterations of this loop are executed before the loop exits. A) Show a pipeline execution diagram for the third iteration of this loop, from the cycle in which we fetch the first instruction of that iteration up to (but not including) the cycle in which we can fetch the first instruction of the next iteration. Show all instructions that are in the pipeline during these cycles (not just those from the third iteration). B) How often (as a percentage of all cycles) do we have a cycle in which all five pipeline stages are doing useful work?

Explanation / Answer

a)

Iteration

2nd LW r1, 0(r1) WB

2nd BEQ r1, r0,LOOP ID EX MEM WB

3 LOOP:LW r1, 0(r1) IF ID EX MEM WB

3 AND r1,r1,r2 IF * ID EX MEM WB

3 LW r1, 0(r1) IF ID EX MEM WB

3 LW r1, 0(r1) IF * ID EX MEM WB

3 BEQ r1, r0,LOOP IF * * ID EX MEM WB

b)As it can be seen from the pipeline execution diagram above, none of the cycles have all five pipeline stages doing useful work

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