library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all ; ent
ID: 3686026 • Letter: L
Question
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity Counter1 is port (
rst, clk : in std_logic;
q : inout std_logic_vector (3 downto 0)
);
end Counter1;
architecture behavioral of Counter1 is
begin
process (rst,clk)
begin
if rst = '1' then q <= "0000";
elsif rising_edge (clk) then q <= q + 2;
end if;
end process;
end behavioral;
ure P6.59. The sip it overrides th wIll eclaration t by 2 as shown in Figure P6,5 by 2 as show ent is clock independent that is, it e 03 02 21 go 0 0 0 0 RST asyn) 1 011 0 1 0 0 0 1 0 1 0 FIGURE P6.59 required library clause, use clauses. on for the counterExplanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity Counter1 is
port (
rst : in std_logic;
clk: in std_logic;
q : inout std_logic_vector(3 downto 0);
);
end Counter1;
architecture Behavioral of Counter1 is
begin
if ( rst = '1' )
then
q <= "0000" ;
else if ( rising_edge(clk) )
then
q <= q+2;
end if ;
end process;
end behavioral;
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