Given: A MIPS-based computer system with 2 GB of main memory that is built on a

Question

Given: A MIPS-based computer system with 2 GB of main memory that is built on a single circuit board. It is designed with a single control signal between the CPU chip and main memory, i.e. one bit of control that is set to one for Read operations and zero for Write operations. How many bits wide is the main memory data bus? How many bits wide is the main memory address bus when 4-banks memory interleaved is used? How long does it takes to fetch 8 words from the memory to MIPS registers using the memory configuration in (b)? Assume that one cycle is required to place the address and one cycle to transfer one word and 15 cycles for memory access. Find the memory bandwidth and compare it to memory bandwidth when no memory interleaved is used.

Explanation / Answer

Answer:

Consider, the MIPS-based computer system with 2 GB of main memory

a)

The word size in the MIPS is 32 bits.

Then, 32-bits data is used to execute the instructions.

Therefore, 32-bit wide main memory data bus is required.

b)

The main memory size = 2GB

The number of bytes in 1GB = 230 bytes.

Then 2GB = 2x 230 = 231 bytes.

Therefore, 31 bits wide is the memory address bus when 4-banks memory interleaved is used.

c)

Consider, one cycle is required to place the address and one cycle to transfer one word and 15 cycles for memory access.

Then, without interleaving the time required to fetch the instructions is 1+1+15= 17 cycles/ word.

When 4-banks memory interleaved is used, then 4 words read in a single burst and takes one clock cycle as each bank is one word wide.

Then the time taken is given as: 2x(1+15+(4x1)) = 2x20 = 40

Therefore, the time required to fetch 8 words from the memory to MIPS registers is 40 cycles.

d)

The memory bandwidth when memory interleaved is used is shown below:

memory bandwidth = the number of byte transfer/ number of clock cycles.

The number of byte transfer = 32 bytes

The number of clock cycles when 4-banks interleaved used = 40 cycles

Then, the memory bandwidth = 32/40 = 0.8 bytes/clock cycle

The memory bandwidth without memory interleaved is used is shown below:

memory bandwidth = the number of byte transfer/ number of clock cycles.

The number of byte transfer = 32 bytes

The number of clock cycles without 4-banks interleaved used = 2x (1+15+1) = 2x17= 34

Then, the memory bandwidth = 32/34 = 0.94 bytes/clock cycle

Therefore, the memory bandwidth with memory interleaved is 0.8 bytes/clock cycle and the memory bandwidth without memory interleaved is 0.94 bytes/clock cycle.

Therefore, the memory bandwidth is more without memory interleaved than the memory bandwidth with memory interleaved.

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