Computer Architecture 4. Do the following problems: pipelined processor has a cl

Question

Computer Architecture 4. Do the following problems: pipelined processor has a clock rate of 2.5 GHz and executes a program with 1.5 million instructions. The pipeline has 5 stages and the instructions are issued at a rate of one per clock cycle. Ignore penalties due to branch instructions and out-of-sequence executions. (x) What is the Speed up of the processor this program compared to a non-pipelined processor? (xx) What is the Throughput (in MIPS) of the pipelined processor? Assume a pipeline has 4 stages: FI (fetch instruction), DA (decode instruction and calculate addresses), FO (fetch operand), EX (execute). Draw a pipeline timing diagram for a sequence of 9 instructions in which the third instruction is a branch that is taken, and there are no b. data dependencies.

Explanation / Answer

Solution:

Number of clock cycles required for non-pipelined processor= 1.5*10^6*5= 7.5 million cycles

Number of clock cycles required for pipelined processor= 1500004 cycles

speedup= 7.5 * 10^6/ 1.500004 * 10^6 = 4.9999866667

Throughput of pipelined= 2.5*10^9= 2500 MIPS

b)

For the sake of convenience, assume instruction 3 branches to instrction 5

c)

(x) resource hazard

Consider an example of four stage pipeline given in part b, Assume the data is stored in cache, which is accessed through a common bus used by all the stages. here when we perform the FI, we need to access the memory and when we perform the FO, then also we need to access the memory. When the first instruction will be performing Fo, the third instruction will not be able to perform FI, so, it will be delayed. This is hazard is resource hazard

(xx) Data Hazard

RAW - consider an example where in two instructions, one instruction is trying ti write the data to the operand another instruction is trying to read the same data.

I1: X = A+B

I2: Y = X+C

Here, I2 will try to read value of X before I1 has written it, this type of hazard is RAW

WAR- consider the following instructions:

I1: X = A + B

I2: A = C

If I2 performs the write on A before I1 could read it will create problem, it type of hazard is WAR data hazard

WAW-consider the example

I1: X = A*B

I2: X = C

Second instruction will take much less time than the first instruction, so, second instruction will write in X before I1, and final write will be performed by I1, which will create problem. This type of hazard is WAW data hazard

(xxx) Control Hazard

Consider a set of 9 instructions, if branch instructions are present in the set of instruction, next instruction to be fetched may not be the instruction in sequence. For example, let 3rd instruction is the branched instruction, and it brances to 7th insruction, then, after the 3rd instruction finish, we will come to know that next instruction to be fetched is 7, so, instruction currently being fetched or decoded are of no use and we will have to flush the pipeline and start fetching 7th instruction. This type of hazard in contro hazard

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Instr. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I1 FI1 DA1 FO1 EX1 I2 FI2 DA2 FO2 EX2 I3 FI3 DA3 FO3 EX3 I4 FI4 DA4 FO3 I5 FI5 DA6 I7 FI7 I4 FI4 DA4 FO4 EX4 I5 FI5 DA5 FO5 EX5 I6 FI6 DA6 FO6 EX6 I7 FI7 DA7 FO7 EX7 I8 FI8 DA8 FO8 EX8 I9 FI9 DA9 FO9 EX9

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