Consider a machine with the following characteristics: the machine has the abili

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Consider a machine with the following characteristics: the machine has the ability to issue multiple operations in a single cycle, all operations take a single cycle to {fetch-decode-execute- commit), and you may not schedule two instructions on the same cycle if they both access the same register and at least one of those accesses is a write. (Two reads is OK.) Now consider the following code segment, which has at least one of each of RAW, WAW, WAR) hazards add r3,r2,r1 # r3 r2 + r1 sub r2,r4,r1 # r2 = r4 - r1 mul r5 , r2,r1 # r5 r2 * r1 div r5,r3, r4 # r5 = r3 / r4 For each type of hazard, identify (1) an instance of the hazard in the above code segment and (2) how register renaming for that hazard would potentially help performance. "An instance of the hazard in the above code segment" should be expressed as "ry between instruction op1 and instruction op2". a RAW (read-after-write) hazard points) Identify an instance of this hazard in the above code segment ii. (2 points) How would register renaming for this hazard potentially help performance? If register renaming would not help, say "Register renaming will not help". (b) WAW (write-after-write) hazard i. (2 points) Identify an instance of this hazard in the above code segment. ii. (2 points) How would register renaming for this hazard potentially help performance? If register renaming would not help, say "Register renaming will not help". (c) WAR (write-after-read) hazard i. (2 points) Identify an instance of this hazard in the above code segment. ii. (2 points) How would register renaming for this hazard potentially help performance? f register renaming would not help, say "Register renaming will not help".

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