Consider the following MIPS code and a 5 stages processor as discussed in class:

Question

Consider the following MIPS code and a 5 stages processor as discussed in class: lw r1, 12(r7) lw r2,16 (r7) add ri,ri, r2 sw r1,4(r5) a. Identify and describe all the data dependencies. b. How many clock cycles does it take to execute this code without any pipelining? How many clock cycles with pipelining, but no bypassing (stalls cause the pipeline to wait until previous instruction is finished)? c. d. How many clock cycles with pipelining and bypassing (data is forwarded to next instruction as soon as is available)? e. Draw the execution diagram for all approaches. f. The CPI (cycles per instruction) is obtained by computing the ratio of total cycles to number of instructions. Compute the CPl for all approaches, and compute their ratio to calculate the improvement gained by the pipeline in each case.

Explanation / Answer

Answer is as follows :

a) Data Dependencies or Data Hazards :

b) The Instruction execution diagram without pipelining is :

So from above diagram we concluded it takes 20 clock cycles without pipelining.

c) Diagram with Pipelining without bypassing :

So from above we conclude that it will take 12 clock cycles with pipelining but no bypassing.

Answer is as follows :

d) Pipeline Diagram of Given Sceanrio with Bypassing :

So the total cycles with full bypassing are 8 clock cycles.

e) Execution Diagram :

1) Without Any Piplining : Provided In part b

2) With Pipelinign Without Bypassing : Provided in part c

3) Full Pipelining : Provided in Part d

f) CPI's

1) Without Any Piplining :

Total Cycles = 20

CPI = 20 / 4 = 5

2) With Pipelinign Without Bypassing :

Total Cycles = 12

CPI = 12 / 4 = 3

3) With full pipelining :

Total Cycles = 8

CPI = 8/4 = 2

Ratio : 5 : 3 : 2

In the b,c,d parts we have :

FI = Fetch Instruction

ID = instruction Decode

EX = Execute instruction

MEM = Memory read/write

WB = Register Read/Write

* = Stalll

if there is any query please ask in comments..

cycles -> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 lw r1,12(r7) FI ID EX MEM WB lw r2,16(r7) FI ID EX MEM WB add r1,r1,r2 FI ID EX MEM WB sw r1,4(r5) FI ID EX MEM WB

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