Consider the following MIPS code that is being executed on the above 5-stage pip

ID: 3709056 • Letter: C

Question

Consider the following MIPS code that is being executed on the above 5-stage pipeline:

Complete the following table showing the timing of the above code on the 5-stage pipeline MIPS processor (IF, ID, EX, MEM, WB). Draw an arrow showing forwarding between the stage that provides the data and the stage that receives the data. Show all stall cycles by placing an X in the box to represent a stall cycle,

MEM

add

sub

MEM

add

sub

Explanation / Answer

Solution:

MEM

add

MEM

sub

MEM

The execution will be finished in 11 cycles.

lw will load the data at MEM that is why ID is delayed in the next instruction until MEM for lw is finished.

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MEM

add

MEM

sub

MEM

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Consider the following MIPS code and a 5 stages processor as discussed in class:

Consider the following MIPS code: LOOP: slt $t2, $zero, $t1 beq $t2, $zero, DONE

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Consider the following MIPS code that is being executed on the above 5-stage pip

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Explanation / Answer

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