4-2 The following module is an example of a combination of blocking and nonblock

Question

4-2 The following module is an example of a combination of blocking and nonblocking assignments. module blocking_nonblocking_mixed; reg a, b, c, d, e; // blocking assignments initial begin end endmodule (a) (b) (c) (d) At what simulation time does each procedural statement execute? Interchange the blocking and nonblocking assignment operators and redo part(a). Replace all nonblocking assignments with blocking assignments and redo part(a). Replace all blocking assignments with nonblocking assignments and redo part (a).

Explanation / Answer

As per the Icarus compiler, these are programs and outputs with time when statements being executed

(a)
PROGRAM
/*
* Do not change Module name
*/
module main;

reg i;
reg a,b,c,d,e;
initial
    begin
        a = #3 1'b0;
        $display("STATEMENT a :: time is %0t",$time);
        b <= #4 1'b1;
        $display("STATEMENT b :: time is %0t",$time);
        c <= #6 1'b0;
        $display("STATEMENT c :: time is %0t",$time);
        d = #7 1'b1;
        $display("STATEMENT d :: time is %0t",$time);
        e = #8 1'b0;
        $display("STATEMENT e :: time is %0t",$time);
        $finish ;
    end
endmodule

OUTPUT:
$iverilog -o main *.v
$vvp main
STATEMENT a :: time is 3
STATEMENT b :: time is 3
STATEMENT c :: time is 3
STATEMENT d :: time is 10
STATEMENT e :: time is 18

(b)

PROGRAM
/*
* Do not change Module name
*/
module main;

reg i;
reg a,b,c,d,e;
initial
    begin
        a <= #3 1'b0;
        $display("STATEMENT a :: time is %0t",$time);
        b = #4 1'b1;
        $display("STATEMENT b :: time is %0t",$time);
        c = #6 1'b0;
        $display("STATEMENT c :: time is %0t",$time);
        d <= #7 1'b1;
        $display("STATEMENT d :: time is %0t",$time);
        e <= #8 1'b0;
        $display("STATEMENT e :: time is %0t",$time);
        $finish ;
    end
endmodule

OUTPUT
$iverilog -o main *.v
$vvp main
STATEMENT a :: time is 0
STATEMENT b :: time is 4
STATEMENT c :: time is 10
STATEMENT d :: time is 10
STATEMENT e :: time is 10

(c)
PROGRAM
/*
* Do not change Module name
*/
module main;

reg i;
reg a,b,c,d,e;
initial
    begin
       a = #3 1'b0;
        $display("STATEMENT a :: time is %0t",$time);
        b = #4 1'b1;
        $display("STATEMENT b :: time is %0t",$time);
        c = #6 1'b0;
        $display("STATEMENT c :: time is %0t",$time);
        d = #7 1'b1;
        $display("STATEMENT d :: time is %0t",$time);
        e = #8 1'b0;
        $display("STATEMENT e :: time is %0t",$time);
        $finish ;
    end
endmodule

OUTPUT
$iverilog -o main *.v
$vvp main
STATEMENT a :: time is 3
STATEMENT b :: time is 7
STATEMENT c :: time is 13
STATEMENT d :: time is 20
STATEMENT e :: time is 28

(d)
PROGRAM
/*
* Do not change Module name
*/
module main;

reg i;
reg a,b,c,d,e;
initial
    begin
       a <= #3 1'b0;
        $display("STATEMENT a :: time is %0t",$time);
        b <= #4 1'b1;
        $display("STATEMENT b :: time is %0t",$time);
        c <= #6 1'b0;
        $display("STATEMENT c :: time is %0t",$time);
        d <= #7 1'b1;
        $display("STATEMENT d :: time is %0t",$time);
        e <= #8 1'b0;
        $display("STATEMENT e :: time is %0t",$time);
        $finish ;
    end
endmodule

OUTPUT
$iverilog -o main *.v
$vvp main
STATEMENT a :: time is 0
STATEMENT b :: time is 0
STATEMENT c :: time is 0
STATEMENT d :: time is 0
STATEMENT e :: time is 0

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