7. Consider a cache with the following parameters: N (associativity) 2, b (block

Question

7. Consider a cache with the following parameters: N (associativity) 2, b (block size) 2 words, W (word size) = 32 bits, C (cache size) = 32 K words. A (address size) = 32 bits. You need consider only word addresses, (a) Show the tag, set, block offset, and byte offset bits of the address. State how many bits are needed for each field (b) What is the size of all the cache tags in bits? (c) Suppose each cache block also has a valid bit (V) and a dirty bit (d) What is the size of each cache set, including data, tag, and status bits? (e) Design the cache using the building blocks in Figure 1 and a small number of two-input logic gates. The cache design must nclude tag storage, data storage, address comparison, data output selection, and any other parts you feel are relevant, Note that the ultiplexer and comparator blocks may be any size (n or p bits wide, respectively), but the SRAM blocks must be 16K × 4 bits, Be sure to include a neatly labeled block diagram You need only design the cache for reads 40 SRAM Figure 1: HW 3 Problem 7

Explanation / Answer

As per chegg guidlines I'm answering the first 4 parts:-

a) word size = 32 bits = 4 B = 22 B

Therefore byte offset field will be of 2 bits.

block size = 2 words.

Therefore block offset field will be of 1 bit.(as it is given that memory is word addressable)

Cache size = 32 K words = 25*210 words = 215 words

Therefore number of blocks = cache size / block size = 215 / 2 = 214

Associativity = 2

Therefore number of sets in the cache = 214 / 2 = 213

Therefore, 13 bits will be there in the set field.

Remaining bits = 32 - (set field + block offset field) = 32 - (13 + 1) =32 - 14 = 18 bits.

Therefore 18 bits will be there in TAG field.

b) Now size of each cache tag = 18 bits

number of cache tags = number of blocks in the cache = 214

Therefore, total size of cache tag =  214 * 18 bits = 24*210*18 bits = 288 K bits.

c) If the tag also has a valid bit and a dirty bit then size of each tag = 18 + 2 = 20bits

Therefore, total size of cache tag =  214 * 20 bits = 24*210*20 bits = 320 K bits.

d) Number of blocks in each set = 2

Therefore number of tag in each set = 2

size of each tag = 20bits (including status bits)

Therefore total tag and status bits in each set = 20 + 20 = 40 bits

Data in each set = 2*2 words[as each block is of 2 words and there are 2 blocks in a set] = 4 words = 4*32 bits [as each word is of 32 bits] = 128 bits

Therefore size of each cache set = 128 + 40 bits = 168 bits.

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