Hi, check the answers that I have for this problem. Please correct any mistakes

Question

Hi, check the answers that I have for this problem. Please correct any mistakes that I may have and provide explanation, Thanks.

3. [8 points] Suppose we have the following latencies for various datapath units. Latency in ps 200 50 50 25 150 120 10 Resource I Mem PC Add Branch Add All MUXs REGs ALU SIGNEXT Shift Left 2 D Mem 250 70 ALU Control (a) [4 pts] Calculate the total latency for a load (b) [4 pts] If we switch to a pipeline architecture, show your work in calculating these values. SOx1R soors instruction. So2oo 5+1S0 +25+Ino so+S t ISOSs (1) what is the clock cycle time ??sors (ii) what is the total latency for a load instruction? [Note for Instructor CRIT] PCSre Add ALU Shift left 2 RegWrite Instruction (25.21] Read PCH/ Read register 1 Read Read register 2 MemWrite instruction [20:16] data 1- ALUSrc Zero MemtoReg M Write Read Instruction Instruction (1511register data2 memory result? Address Read Write data Registers Data Instruction [15:0] 16 Sign. 32 extend ALU MemRead Instruction (5:0] ALUOp

Explanation / Answer

Answer is as follows :

After Examining we will find that :

a) To calculate the total latency for load instruction we add the various resources that are used in load instruction together in no-pipelinig.

So the resources used by you are correct.

b)

i) The answer 250 ps is correct for load instruction , we take highest number of latency in pipelining.

ii) The answer is incorrect, Because we know that the processor is of 5 stage pipelining.

So we multiply 250 by 5 not by 10.

So the correct answer is 250 * 5 = 1250 ps.

if there is any query please ask in comments...

Related Questions

Navigate

• Browse (All)
• Browse H
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.