a Register with Synchronous Reset and Paralel Load: Use the D Flip-Flop to creat
ID: 3709790 • Letter: A
Question
a Register with Synchronous Reset and Paralel Load: Use the D Flip-Flop to create esign (4-bit shift register) as in 4.2.4, this time with parallel load function instead of serial n your new design, you will have 4-bit data input instead of one. Figure 4.2.3 depicts With the desired inputs. Explain the advantages and disadvantages of serial and parallel loads. (Again, no need for designing the 7-seament LED decoder here as well, the similar d load. Thus i the symbol decode r will be used during the experimental work.) -ul 30- 7 Segment segoutl7.0 Decoder _Datal3.? 4-bit Register CLK SYNC RST Figure 4.2.3. 4-bit Register with Parallel LoadExplanation / Answer
module stimlulus ;
reg clk;
reg rst;
reg load;
reg [3:0] Data;
wire [6:0] Out;
// during instantiataion we are overiding the parameter N with 2
// So the module is the 2 bit left shift register
shift_register_parallel_load DUT (
.clk (clk),
.rst(rst),
.load(load),
.Data(Data),
.Out(Out)
);
integer i , j;
initial // clock generation logic
begin
clk = 0;
forever begin
#5 clk = ~clk;
end
end
always @ (posedge clk)
$display("rst = %b load = %b, Data = %d Out = %h", rst, load, Data, Out);
initial begin // dump creation for waveform
$dumpfile("dump.vcd");
$dumpvars;
end
initial // applying the inputs to module
begin
load = 1'b0;
rst = 1'b0;
@(negedge clk);
rst = 1'b1;
repeat(2)
@(negedge clk);
rst = 1'b0;
for(j = 0 ; j < 10; j = j + 1)
begin
load = 1'b1;
Data = j ;
@(negedge clk);
load = 1'b0;
repeat(4)
@(negedge clk);
end
$finish;
end
endmodule
module seven_segement(
input [3:0] BCD_IN,
output [6:0] HEX0
);
//internal wire signal
reg [6:0] HEX0;
always @(BCD_IN)
begin
case(BCD_IN)
4'd0 : HEX0 = 7'b111_1110; // represents 0 in SSD
4'd1 : HEX0 = 7'b011_0000; // represents 1 in SSD
4'd2 : HEX0 = 7'b110_1101; // represents 2 in SSD
4'd3 : HEX0 = 7'b111_1001; // represents 3 in SSD
4'd4 : HEX0 = 7'b011_0011; // represents 4 in SSD
4'd5 : HEX0 = 7'b101_1011; // represents 5 in SSD
4'd6 : HEX0 = 7'b101_1111; // represents 6 in SSD
4'd7 : HEX0 = 7'b111_0000; // represents 7 in SSD
4'd8 : HEX0 = 7'b111_1111; // represents 8 in SSD
4'd9 : HEX0 = 7'b111_1011; // represents 9 in SSD
endcase
end
endmodule
module DFF (
input clk,
input rst,
input D,
output reg Q
);
always @ (posedge clk)
begin
if (rst)
Q <= D;
else
Q <= D;
end
endmodule
module shift_register_parallel_load (
input clk, rst, load,
input [3:0] Data,
output [6:0] Out
);
wire [3:0] Din, Q;
assign Din = load ? Data : {1'b0, Q[3:1]};
DFF U_3 (.clk(clk), .rst(rst), .D(Din[3]), .Q(Q[3]));
DFF U_2 (.clk(clk), .rst(rst), .D(Din[2]), .Q(Q[2]));
DFF U_1 (.clk(clk), .rst(rst), .D(Din[1]), .Q(Q[1]));
DFF U_0 (.clk(clk), .rst(rst), .D(Din[0]), .Q(Q[0]));
seven_segement U_4 (.BCD_IN(Q), .HEX0(Out));
endmodule
/******************** OUTPUT OF FILE ********************
rst = 0 load = 0, Data = x Out = xx
rst = 1 load = 0, Data = x Out = xx
rst = 1 load = 0, Data = x Out = xx
rst = 0 load = 1, Data = 0 Out = xx
rst = 0 load = 0, Data = 0 Out = 7e
rst = 0 load = 0, Data = 0 Out = 7e
rst = 0 load = 0, Data = 0 Out = 7e
rst = 0 load = 0, Data = 0 Out = 7e
rst = 0 load = 1, Data = 1 Out = 7e
rst = 0 load = 0, Data = 1 Out = 30
rst = 0 load = 0, Data = 1 Out = 7e
rst = 0 load = 0, Data = 1 Out = 7e
rst = 0 load = 0, Data = 1 Out = 7e
rst = 0 load = 1, Data = 2 Out = 7e
rst = 0 load = 0, Data = 2 Out = 6d
rst = 0 load = 0, Data = 2 Out = 30
rst = 0 load = 0, Data = 2 Out = 7e
rst = 0 load = 0, Data = 2 Out = 7e
rst = 0 load = 1, Data = 3 Out = 7e
rst = 0 load = 0, Data = 3 Out = 79
rst = 0 load = 0, Data = 3 Out = 30
rst = 0 load = 0, Data = 3 Out = 7e
rst = 0 load = 0, Data = 3 Out = 7e
rst = 0 load = 1, Data = 4 Out = 7e
rst = 0 load = 0, Data = 4 Out = 33
rst = 0 load = 0, Data = 4 Out = 6d
rst = 0 load = 0, Data = 4 Out = 30
rst = 0 load = 0, Data = 4 Out = 7e
rst = 0 load = 1, Data = 5 Out = 7e
rst = 0 load = 0, Data = 5 Out = 5b
rst = 0 load = 0, Data = 5 Out = 6d
rst = 0 load = 0, Data = 5 Out = 30
rst = 0 load = 0, Data = 5 Out = 7e
rst = 0 load = 1, Data = 6 Out = 7e
rst = 0 load = 0, Data = 6 Out = 5f
rst = 0 load = 0, Data = 6 Out = 79
rst = 0 load = 0, Data = 6 Out = 30
rst = 0 load = 0, Data = 6 Out = 7e
rst = 0 load = 1, Data = 7 Out = 7e
rst = 0 load = 0, Data = 7 Out = 70
rst = 0 load = 0, Data = 7 Out = 79
rst = 0 load = 0, Data = 7 Out = 30
rst = 0 load = 0, Data = 7 Out = 7e
rst = 0 load = 1, Data = 8 Out = 7e
rst = 0 load = 0, Data = 8 Out = 7f
rst = 0 load = 0, Data = 8 Out = 33
rst = 0 load = 0, Data = 8 Out = 6d
rst = 0 load = 0, Data = 8 Out = 30
rst = 0 load = 1, Data = 9 Out = 7e
rst = 0 load = 0, Data = 9 Out = 7b
rst = 0 load = 0, Data = 9 Out = 33
rst = 0 load = 0, Data = 9 Out = 6d
rst = 0 load = 0, Data = 9 Out = 30
**************************************************************/
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