8. [18 points] Suppose we have a memory and a direct-mapped cache with the follo

Question

8. [18 points] Suppose we have a memory and a direct-mapped cache with the following * Memory is byte addressable * Memory addresses are 16 bits The cache has 8 blocks * Each cache block holds 16 bytes of data a) 3 points] In the spaces below, indicate how the 16 address bits are allocated to the offset, index, and tag parts of the address used to reference the cache offset bits tag bits index bits. b) [12 points] Below is a sequence of four binary memory addresses in the order they are used to reference memory. Assume that the cache is initially empty. For each reference, write down the tag and index bits and circle either hit or miss to indicate whether that reference is a hit or a miss. Index Hit Miss (circle) Hit Hit Hit Hit Memory address Tag Miss Miss Miss Miss 0010 1101 1011 0011 0010 1101 1011 1000 1010 1010 1010 1011 c) B points Supose the cache access time is 15ns, main memory access time is 220ns, and the cache hit rate is 95%. Assuming parallel (overlapped) access (CPU starts the data request in parallel to both cache and to main memory at the same, so if a cache missing occurs, we don't have to add this cache search time to the memory access), what is the average access time for the processor to access an item?

Explanation / Answer

Suppose we have a memory and a direct-mapped cache with the following characteristics.

1. In the spaces below, indicate how the 16 address bits are allocated to the offset,
index, and tag parts of the address used to reference the cache:4 offset bits,9 tag bits and 3 index bits.

2. Below is a sequence of four binary memory address in the order they are used to reference memory. Assume that the cache is initailly
empty. For each reference, write down the tag and index bits and circle either hit or miss to indicate whether that refernece is a hit or a miss

Memory address Tag Index Hit / Miss (circle)
0010 1101 1011 0011 0010 1101 1 011 Hit Miss
0000 0110 1111 1100 0000 0110 1 111 Hit Miss
0010 1101 1011 1000 0010 1101 1 011 Hit Miss
1010 1010 1010 1011 1010 1010 1 010 Hit Miss

3.Suppose the cache access time is 15ns, main memory access time is 220ns, and the cache hit rate is 95%. Assuming parallel(overlapped) access
(CPU starts the data reuest in parallel to both cache and to main memory at the same, so if a cache missing occurs, we dont have to add this cache
search time to the memory access, what is the average access time for the processor to access an item?

The average read access time for the processor to access an item is
= 9.5 * 15 + 0.2*220
= 186.5

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