Sample Exam Questions The latest processor in the market has two levels of data
ID: 3720619 • Letter: S
Question
Sample Exam Questions The latest processor in the market has two levels of data caches, with the characteristics shown below. You can also assume that it takes 50 clock cycles to request and complete a 32-byte transfer between main memory and the L2 cache .Find the average memory access time (AMAT) for both the L2 and L1 cache. Also find the number of storage bits required for each cache assuming 48 bit addresses. Level Data Size Block Size 8bytes 32bytes Associativity 1-way4-way Hit Time Miss Rate Ll ?2 32KB 256KB 1 cycle 19 cycles 5% 2%Explanation / Answer
Address size = 48 bits
L1 CACHE:
cache size = 32KB = 215 bytes
block size = 8 bytes = 23 bytes
Therefore number of blocks in the cache = 215/23 = 212
Associativity = 1 way
Therefore number of sets = 212
As block size is 23 bytes therefore offset field will be of 3 bits.
As number of sets is 212 so, index field will be of 12 bits.
Remaining bits = 48 - ( 12 + 3) = 48 - 15 = 33 bits
Therefore TAG field will be of 33 bits.
Therefore number of storage bits required = number of blocks*TAG size = 212*33 bits = 135168 bits.
AMAT = 0.95*1 + 0.05*0.98(1+19) + 0.05*0.02(1 + 19 + 50)
= 0.95 + 0.98 + 0.07 = 2 clock cycles
L2 CACHE:
cache size = 256KB = 218 bytes
block size = 32 bytes = 25bytes
Therefore number of blocks in the cache = 218/25 = 213
Associativity = 4 way
Therefore number of sets = 213/22 = 211
As block size is 25 bytes therefore offset field will be of 5 bits.
As number of sets is 211 so, index field will be of 11 bits.
Remaining bits = 48 - ( 11 + 5) = 48 - 16 = 32 bits
Therefore TAG field will be of 32 bits.
Therefore number of storage bits required = number of blocks*TAG size = 213*32 bits = 262144 bits.
AMAT = 0.98*19 + 0.02(19 + 50)
= 18.62 + 1.38 = 20.38 clock cycles.
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