Assume a direct mapped cache design that uses the following specifications. Tota

Question

Assume a direct mapped cache design that uses the following specifications. Total memory size is 32 bytes (5 bit memory addresses). Cache uses blocks of size 4 bytes, and the cache holds 4 blocks (i.e., 16 bytes).

Cache contents during operation are as follows:

?--Tag?------>|??-----------------------Contents? ----------------------------->

1

0X7E

0X8F

0X9A

0X91

1

0X6B

0X5E

0X2C

0X1A

0

0X3A

0X0C

0X4D

0X8B

1

0X3F

0X99

0X33

0X0D

What data is retrieved when the following addresses are used?

- 10011

- 10001

- 10101

- 01001

- 11110

1

0X7E

0X8F

0X9A

0X91

1

0X6B

0X5E

0X2C

0X1A

0

0X3A

0X0C

0X4D

0X8B

1

0X3F

0X99

0X33

0X0D

Explanation / Answer

Solution :

Here 2 bits are used for offset of a block.
as block size is 4Bytes, 2 bits will be needed as offset.

There are 4 blocks in cache. Hence 2 bits are used as index bits.

And 1 bit is used as tag bit.

10011 -> block = 00, tag = 1, and offset = 11. Hence data = 0x91
10001 -> block = 00, tag = 1, offset = 01 . Hence data = 0x8F
10101 -> block = 01, tag = 1, offset = 01 . Data = 0x5E
01001 -> block = 10, tag = 0, offset = 01 . Data = 0x0C
11110 -> block = 11, tag = 1, offset = 10 . Data = 0x33

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