computer architecture 3. (2 pts) There are two types of RAM. SRAM tul tau 4. (30

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computer architecture

3. (2 pts) There are two types of RAM. SRAM tul tau 4. (30 pts) Here is a series of memory reads. The address references are given as word addresses: 1,2,22, 4,8, 20, 5, 6, 17, 14, 7,4,8, 19, 5,6,22, 9, 11, 12, 56, 4, 5, 6, 43, 9, 17, 12, 3, 4, 8, 20, 25, 12, 5, 6, 8, 9, 48, 4, 8 For each of the following, cachesI miss Direct mapped cache with 16 one-word blocks. . Direct mapped cache with four-word blocks and total size of 16 words. . Two-way associative cache with one-word blocks and a total size of 16 words. Assume LRU replacement.

Explanation / Answer

4) Hit/Miss Ratio

A) Direct mapped cache with 16 one-word blocks

    1 word=20 =0 offset

    16 block=24 =4 index

     Remainging 28 bits in 32 bit for tag.

So,hit/miss calculation based on same tag and index value of two address references(if same=hit else miss)

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B) Direct mapped cache with 16 4-word blocks

    1 word=21 =1offset

    16 block=24 =4 index

     Remainging 27 bits in 32 bit for tag.

So,hit/miss calculation based on same tag and index value of two address references and indexes(if same=hit else miss)

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C)Two way associative

Memory Binary Tag Index Hit/Miss 1 00000001 0000 0001 miss 2 00000010 0000 0010 miss 22 00010110 0001 0110 miss 4 00000100 0000 0100 miss 8 00001000 0000 1000 miss 20 00010100 0001 0100 miss 5 00000101 0000 0101 miss 6 00000110 0000 0110 miss 17 00010001 0001 0001 miss 14 00001110 0000 1110 miss 7 00000111 0000 0111 miss 4 000001000 0000 0100 hit 8 00001000 0000 1000 hit 19 00010011 0001 0011 miss 5 00000101 0000 0101 hit 6 00000110 0000 0110 hit 22 00010110 0001 0110 hit 9 00001001 0000 1001 miss 11 00001011 0000 1011 miss 12 00001100 0000 1100 miss 56 00111000 0011 1000 miss 4 00000100 0000 0100 hit 5 00000101 0000 0101 hit 6 00000110 0000 0110 hit 43 00101011 0010 1011 miss 9 00001001 0000 1001 hit 17 00010001 0001 0001 hit 12 00001100 0000 1100 hit 3 00000011 0000 0011 miss 4 00000100 0000 0100 hit 20 00010100 0001 0100 hit 25 00011001 0001 1001 miss 12 00001100 0000 1100 hit 5 00000101 0000 0101 hit 6 00000110 0000 0110 hit 8 00001000 0000 1000 hit 9 00001001 0000 1001 hit 48 00110000 0011 0000 miss 4 00000100 0000 0100 hit 8 00001000 0000 1000 hit

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