Problem 3. Control and Data Hazards A benchmark in a five-stage pipelined proces
ID: 3737747 • Letter: P
Question
Problem 3. Control and Data Hazards A benchmark in a five-stage pipelined processor has the following characteristics: 26% ALU instructions, 14% of these instructions are followed by branch instructions that need the result 23% load instructions 38% of the loads are followed by instructions that use the data being loaded. 15% of these loads are followed by stores that write in memory the data being loaded. 12% of these loads are followed by branches that need the data 14% store instructions 19% floating point instructions, and 18% branch instructions 54% of these branches are taken This processor's CPlint and CPlFP are equal to 1 and 3.1, respectively (when there are no hazards). Please compute the overall CPl. Please assume that there is prediction (not taken).Explanation / Answer
In five stage pipeline normally the stages will be instruction fetch, instruction decode , execution , memory access , write back.
Instruction fetch :- in this stage we fetch the instruction.
Instruction decode :- in this stage we decode the instruction and try to find out what we need to perform.
Execution:- here arithmetic operation will be performed.
Memory access:- all the load and store instructions use this phase to load in memory or from memory.
Write back:- finally all the instruction which need the result of another instruction wait of the competition of instruction.
Note :-1) Normally in parallel pipelining we can complete each instruction in one CPI but whenever dependency comes it create problem and increase average CPI.
2) Whenever dependency comes we need to wait until write back. so those time it takes 3 cpi .
Overall CPI = .26( .86 + .14 * 3) *1 +.23( .88 + .12*3) *1 +.14 *1 + .19 *3.1 +.18 (.54 * 3 +.46 )
=1.7214
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