Question 22 pts The output of an OR gate is connected directly to the input of a

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Question 22 pts

The output of an OR gate is connected directly to the input of an AND gate. The other AND gate input is a constant "Enable" HIGH. A technician checks the inputs to the OR gate and notes a HIGH and LOW. The output of the OR gate is noted as being a HIGH. The "Enable" HIGH input to the AND gate is verified as normal. The technician checks the OR gate input to the AND gate and observes a LOW or no voltage condition. Of the probable causes listed, select the one that most likely is the problem. Assume CMOS gates.

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Question 32 pts

The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates:

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Question 42 pts

The operations of addition and subtraction of signed binary numbers may be accomplished with parallel full-adders, provided that:

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Question 52 pts

The process of designing a synchronous counter that will count in a nonbinary sequence is primarily based on:

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Question 62 pts

The type of counter where each flip-flop provides the CLK input to the next flip-flop is referred to as a ________ counter.

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Question 72 pts

The primary differences between a decoder and an encoder are:

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Question 82 pts

A demultiplexer accepts data from:

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Question 92 pts

Synchronous (parallel) counters do not experience the delay problems encountered with asynchronous (ripple) counters because:

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Which of the following best describes volatile memory?

Explanation / Answer

which of the following best desribes volatile memory???

Memory that loses stored information when electrical power is removed.

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