Synthesis with HDL CPE 315 Name: J# Note that there are four problems in this ex
ID: 3739633 • Letter: S
Question
Synthesis with HDL CPE 315 Name: J# Note that there are four problems in this exam Problem 1 (28 points) Test #2, Spring, 2018 Time, (70 minutes) On this sheet, CIRCLE T for a true statement and F for a false statement T F 1) The presence of a sensitivity list in a process is equivalent to the presence of an implicit WAIT ON sensitivity list. T F 2) When the statement (WAIT ON clk FOR 3 NS:) is used in a process, it means that the simulator will stop if no event occurs on the elk within 3 NS. T F 3) The IF statement can be used outside a process statement, but it must be insid architecture. T F 4) We are not allowed to multiply the physical type resistance directly with the physical type capacitance when computing the delay in NS. T F 5) A process with a sensitivity list must contain at least one wait statement. T F 6) A subtype without constraint has the same set of values as the base type. T F 7) Some values of the expression used in the case statement can be covere in case statement.Explanation / Answer
Answer)
1) The presence of a sensitivity list in a process is equivalent to the presence of an implicit WAIT on sensitivity list.
This is True as a process with sensitivity list always suspends at the end of the process and the presence of a sensitivity list in a process is equivalent to the presence of an implicit WAIT on sensitivity list.
2) When the statement (WAIT ON clk FOR 3 NS;) is used in a process, it means that the simulator will stop if no event occurs on the clk within 3 NS.
This is True as WAIT ON clk means that the process will wait for the event to occur for 3 NS.
3) The IF-statement can be used outside a process statement, but it must be inside architecture.
This is False as the if-then-else statement must be in a process and not outside.
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.