Synthesis with HDL CPE 315 Name: He Test #1, Fall, 2018 Time, (60 minutes) Note
ID: 3754061 • Letter: S
Question
Synthesis with HDL CPE 315 Name: He Test #1, Fall, 2018 Time, (60 minutes) Note that there are three problems in this exam. Problem 1, (28 points) On this sheet, CIRCLE T for a true statement and F for a false statement. TF1) In structural modeling of large circuits, it is necessary to have the circuit diagram T F 2) Unlike C language, the order of VHDL statements in an ARCHITECTURE is not important when modeling circuits. F 3) In structural modeling, ports can be mapped by name or by position, and the T F 4) Entity ports cannot be treated as variables. TF 5) The order of components in an ARCHITECTURE is important in structural T F 6) The predefined type BOOLEAN has the literals 'FALSE' and TRUE F 7) It is advisable to model a 3-input NAND gate using the following architecture order of the ports is important when mapping by name. modeling of circuits. ARCHITECTURE nand3 arch OF nand3 IS BEGIN Nand3_output A NAND B NAND C AFTER 2 NS: END ARCHITECTURE nand3_arch:Explanation / Answer
Q1) TRUE [Reason - to reduce any logic errors in design and manufacturing of circuits to be implemented in IC chips]
Q2) FALSE - Order of stmts matters
Q3) TRUE
Q4) FALSE - They can be treated as variables
Q5) TRUE
Q6) TRUE - Boolean contains TRUE and FLASE values
Please let me know in case of any clarifications required. Thanks!
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