Computer Architecture class: Memory hierarchy For a 64-Kbyte, 2-way set associat

Question

Computer Architecture class: Memory hierarchy

For a 64-Kbyte, 2-way set associative cache, with 32-byte cache blocks, study the cache miss rate for the following loops, assuming: The cache initially is empty; Integers are 4 bytes long and two-dimensional arrays are stored in row-major order. Partially credit may be awarded, if intermediate results are shown. Calculate the cache miss rate? If the cache is only 3-Kbyte in size, describe how the loop transformations that we have studied in class can reduce cache misses for the above loops.

Explanation / Answer

1- cache miss rate = 25%

2- A cache line is a contiguous chunk of memory. if cache is 3-kbyte in size. This means that 3 contiguous bytes are always loaded into the cache at a time, namely whenever a miss occurs.

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