Computer Architecture course question. An ISA supports an 8-bit. Byte-addressabl

Question

Computer Architecture course question.

An ISA supports an 8-bit. Byte-addressable virtual address space. The corresponding physical memory has only 128 bytes. Each page contains 16 bytes. A simple, one-level translation scheme is used and the page table resides in physical memory. The initial contents of the pages of physical memory are shown below. A three-entry translation look aside buffer that uses Least Recently-Used (LRU) replacement is added to this system. Initially, this TLB contains the entries for pages 0. 2. and 13. For the following sequence of references, put a circle around those that generate a TLB hit and put a rectangle around those that generate a page fault. What is the hit rate of the TLB for this sequence of references? References (to pages): 0, 13, 5, 2, 14, 14, 13, 6, 6, 13, 15, 14, 15, 13, 4, 3. At the end of this sequence, what three entries are contained in the TLB? What are the contents of the 8 physical pages?

Explanation / Answer

References (to pages): (0), (13), 5, 2, [14], (14), 13, [6], (6), (13), [15], 14, (15), (13), [4], 3.
TLB Hit Rate = 7/16
(a) At the end of this sequence, what three entries are contained in the TLB?
Solution:   4, 13, 3
(b) What are the contents of the 8 physical frames?
Solution:   Pages 14, 13, 3, 2, 6, 4, 15, Page table

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