Computer Architecture problem Problem 2. Your task is to compare the memory effi

Question

Computer Architecture problem

Problem 2.

Your task is to compare the memory efficiency of the four ISAs below:

Accumulator—All operations occur between a single register and a memory location;

Memory-memory—All three operands of each instruction are in memory;

Stack—All operations occur on top of the stack. Only push and pop access memory. All

other instructions remove their operands from stack and replace them with the result. The implementation uses a stack for the top two entries. Accesses that use other stack positions are memory references;

Load-store—All operations occur in registers, and register-to-register instructions have three operands per instruction. There are 16 general-purpose registers, and register specifiers are 4 bits long.

To measure memory efficiency, make the following assumptions:

The opcode is always 1 byte (8 bits);

All memory addresses are 2 bytes (16 bits);

All data operands are 4 bytes (32 bits);

All instructions are an integer number of bytes. There are no other optimizations to

reduce memory traffic, and variables A, B, C, and D are initially in memory.

Invent your own mnemonics and write the best equivalent assembly language code for the high- level-language fragment given below. Write the four code sequences for

A = B + C; B = A + C; D = A - B;

Calculate the instruction bytes fetched and the memory-data bytes transferred.

Which ISA is most efficient as measured by code size?

Which ISA is most efficient as measured by total memory bandwidth required (code +

data)?

Explanation / Answer

Which ISA is most efficient as measured by code size?

Ans) Three address load store architecture is the most efficient by code size.

Code for different ISA :

Stackbased Architecture-

push B
push C
op
pop A
push A
push C
op
pop B
push A
push B
op
pop D

2.One-address machine:

LOAD B
OP C
STORE A
LOAD A
OP C
STORE B
LOAD A
OP B
LOAD D

3.two-address machine

OP B,C
STORE A,B
OP A,C
STORE B,A
OP A,B
STORE D,A

4. three-address machine:

OP A,B,C
OP B,A,C
OP D,A,B

5. CODE for three-address load-store machine whose sources and destination are registers.

LOAD R1,B
LOAD R2,C
OP R3,R1,R2
ST R3,A
OP R1,R3,R2
ST R1,B
OP R2,R3,R1
ST R3,D

Which ISA is most efficient as measured by total memory bandwidth required (code + data)?

Three address load store architecutre is most efficient measured by total memory bandwidth required (code + data).

Data calculated:

1. IN stack based architecutures 12 instruction bytes are fetched

memory-data bytes are 9*2=18 bytes.

2.one-address machine: instruction bytes:9

memory-data 9*2=18 bytes

3. in two address machine :instructionbytes :6

memory -data 12*2=24

4. in three address machine :instruction bytes=3

memory to data :9*2=18

5. In three-address load-store machine whose sources and destination are registers.

instruction bytes:8

memory to data :14 bytes

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