A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1

Question

A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz
clock. Instruction statistics in a large program are as follows:
Branch 20%
Load 20%
Store 10%
Computational instructions 50%
Estimate the rate of instruction execution in each of the following cases:
(a) Access to the memory is always completed in 1 clock cycle.
(b) 90% of instruction fetch operations are completed in one clock cycle and 10% are
completed in 4 clock cycles. On average, access to the data operands of a Load or Store
instruction is completed in 3 clock cycles

Figure 5.4:https://www.dropbox.com/s/rxmtcq05bpxre7l/5.4.png?dl=0

Explanation / Answer

(a) Since each memory access completes in one clock cycle, each instruction will take 5 cycles to complete on the 5-stage RISC hardware.
Therefore, CPI = 5.
Since:
Execution time = (Number of Instructions * CPI) / Clock Rate
Therefore:
Instruction Execution Rate = Number of Instructions / Execution Time = Clock Rate / CPI = 1 GHz / 5 = 109 / 5 = 200 million instructions per second

(b) Let us look at each stage individually:
Stage-1: 90% of instruction fetches take 1 cycle, 10% of fetches take 4 cycles.
Therefore, CPI for stage-1 = (0.9*1) + (0.1*4) = 1.3
Stage-2: Each instruction spends one cycle in stage-2.
Therefore, CPI for stage-2 = 1
Stage-3: Each instruction spends one cycle in stage-3.
Therefore, CPI for stage-3 = 1
Stage-4: Load/store instructions require 3 cycles for memory access, all other instructions take 1 cycle (no memory access).
Therefore, CPI for stage-4 = (0.2 + 0.1)(3) + (0.2 + 0.5)(1) = 1.6
Stage-5: Each instruction spends one cycle in stage-5. Therefore, CPI for stage-5 = 1

Since all the instructions are executed in a sequential fashion (no pipelining):
Total CPI = 1.3 + 1 + 1 + 1.6 + 1 = 5.9 Instruction Execution Rate = Clock Rate / CPI = 1 GHz / 5.9 = 169.5 million instructions per second

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