1) Suppose that we have three different cache designs available. In all three ca
ID: 3765034 • Letter: 1
Question
1) Suppose that we have three different cache designs available. In all three cache designs, the cache lines can each hold a block that is 2^3=8 bytes, and the total number of cache lines is 2^5=32. The first design uses direct mapping, the second design uses associative mapping, and the third design uses 16-way set associative mapping. Given the following 10-bit real memory address:
1010101001,
a) show how the bits (the actual bit values) are split among the different fields utilized
in each mapping scheme (i.e., which bits are used as the tag, which bits are used as the set
number, which bits are used as the line number, and which bits are used as the offset)?
Direct Mapping Associative Mapping Set-Associative Mapping
Tag Line Offset Tag Offset Tag Set Offset
b) What is the total cache size in bytes for these three caches designs?
c) For each of these three cache designs, describe the location, i.e., the address of the
cache line/block where the data may be located in the cache? Describe how we determine
if an address issued by the CPU has a corresponding entry in the cache?
d) Draw a diagram showing how each of these three cache designs is organized.
Explanation / Answer
Consider the following TT
A | B | C || D | E | F
--+---+---++---+---+--
O | 0 | 0 || 0 | 0 | 0
0 | 0 | 1 || 1 | 0 | 0
0 | 1 | 0 || 1 | 0 | 0
0 | 1 | 1 || 1 | 1 | 0
1 | 0 | 0 || 1 | 0 | 0
1 | 0 | 1 || 1 | 1 | 0
1 | 1 | 0 || 1 | 1 | 0
1 | 1 | 1 || 1 | 0 | 1
Here is the circuit diagram for this truth table.
Here it is redrawn in a more schmatic style.
Finally, it can be redrawn in a more abstract form.
Before a PLA is manufactured all the connections are specified. That is, a PLA is specific for a given circuit. It is somewhat of a misnomer since it is notprogrammable by the user
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