Consider the following instructions at the given addresses in the memory: 0x0000
ID: 3766013 • Letter: C
Question
Consider the following instructions at the given addresses in the memory:
0x0000.1000 Load R1, 0(R0)
0x0000.1004 Add R2, R1, #5
0x0000.1008 And R3, R2, #0x0000.0010
0x0000.100C Store R3, 4(R4)
0x0000.1010 Add R5, R2, R3
Initially, R0 and R4 contain 0x0000.2000 and 0x1000.2000, respectively. These instructions are executed in a computer that has a five-stage pipeline as described in Chapter 6. The first instruction is fetched is clock cycle 1.
(a) Assume all memory access operations are cache hit. Complete the diagram that represents the flow of the instructions through the pipeline. How many cycles does it take to execute all the instructions if data forwarding is allowed? Also add marks to the diagram to indicate where data forwarding is used.
Cycle 1 2 3 …
Load R1, 0(R0) F D …
Add R2, R1, #5 F …
And R3, R2, #0x0000.0010 …
Store R3, 4(R4)
Add R5, R2, R3
(b) Assume only memory accesses to addresses 0x0000.1000 – 0x0000.4000 are cache hit. Accesses to all other addresses are cache miss, which take 3 cycles to complete. Repeat Problem (a) to draw a diagram that represents the flow of the instructions through the pipeline. How many cycles does it take to execute all the instructions if data forwarding is allowed? Also add marks to the diagram to indicate where data forwarding is used.
Explanation / Answer
accoring to given data
R0=0.2
R1=5
R2=5.2
R3=5
R4=4.8
R5=10.2
Total cycles are required 5 according to given data
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.