10. What is true about the following code sequence: addi $t1, $t0, #1 addi $t2,
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Question
10. What is true about the following code sequence:
addi $t1, $t0, #1
addi $t2, $t0, #2
addi $t3, $t0, #2
addi $t3, $t0, #4
addi $t5, $t0, #5
a. Must stall on the addi results
b. Can avoid stalls using only forwarding
c. Can execute without stalling or forwarding
d. None of the above
11. What is true about the following code sequence:
lw $t0, 0($t0)
add $t1, $t0, $t0
a. Must stall on the addi results
b. Can avoid stalls using only forwarding
c. Can execute without stalling or forwarding
d. None of the above
12. Pipelining improves CPU performance due to
a. reduced memory access time
b. increased clock speed
c. the introduction of parallellism
d. additional functional units
e. None of the answers above is correct
13. Parallel programs: Which speedup could be achieved according to Amdahl´s law for infinite number of processors if 5% of a program is sequential and the remaining part is ideally parallel?
a. Infinite speedup
b. 5
c. 20
d. 50
e. None of the answers above is correct.
14. Match the memory hierarchy element with the appropriate phrase below.
15. Both large block sizes and prefetching may reduce compulsory misses.
True or False
16. Which operations can isolate a field in a word?
a. AND
b. A shift left followed by a shift right
c. Neither
d. Both
17. When a cache block has been modified since being read from main memory
a. the valid bit is set
b. the dirty bit is set.
c. All of the above
d. None of the above.
18. Which of the following statements are generally true? More than one can apply.
a. Elements at lower levels of the memory hierarchy are generally faster than those at higher levels.
b. Most of the capacity of the memory hierarchy is at the lowest level.
c. On a read, the value returned depends on which blocks are in the cache
d. Caches take advantage of temporal locality
19. Simultaneous multithreading uses threads to improve resource utilization of a dynamically scheduled, out-of-order processor.
True or False
A cache for a cache Main Memory A cache for a main memory L2 cache A cache for disks TLB A cache for page table entries L1 cacheExplanation / Answer
10. What is true about the following code sequence:
addi $t1, $t0, #1
addi $t2, $t0, #2
addi $t3, $t0, #2
addi $t3, $t0, #4
addi $t5, $t0, #5
a. Must stall on the addi results
b. Can avoid stalls using only forwarding
c. Can execute without stalling or forwarding
d. None of the above
11. What is true about the following code sequence:
lw $t0, 0($t0)
add $t1, $t0, $t0
a. Must stall on the addi results(I hope this is add)
b. Can avoid stalls using only forwarding
c. Can execute without stalling or forwarding
d. None of the above
12. Pipelining improves CPU performance due to
a. reduced memory access time
b. increased clock speed
c. the introduction of parallellism
d. additional functional units
e. None of the answers above is correct
13. Parallel programs: Which speedup could be achieved according to Amdahl´s law for infinite number of processors if 5% of a program is sequential and the remaining part is ideally parallel?
a. Infinite speedup
b. 5
c. 20
d. 50
e. None of the answers above is correct.
14. Match the memory hierarchy element with the appropriate phrase below.
Answer:
A cache for a cache ----L1 cache
A cache for a main memory ----L2 cache
A cache for disks ---Main Memory
A cache for page table entries ---TLB
15. Both large block sizes and prefetching may reduce compulsory misses.
True or False
Answer: False
A cache for a cache Main Memory A cache for a main memory L2 cache A cache for disks TLB A cache for page table entries L1 cacheRelated Questions
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