1) translate the following C code to MIPS assembly code. Use a minimum number of
ID: 3770513 • Letter: 1
Question
1) translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, I, and j are in registers $S0, $S1, $t0, and $t1, respectively. Also, assume that register $S2 holds the base address of the array D.
for(i = 0; i < a; i++)
for (j = 0; j < b; j++)
D[4*j] = i + j;
2)For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.
a) What is the cache block size (in words)? [2 points]
b) How many entries does the cache have? [2 points]
c) What is the ratio between total bits required for such a cache implementation over the data storage bits? [2 points]
Starting from power on, the following byte-addressed cache references are recorded
Address 0,4,16,132,232,160,1024,30,140,3100,180,2180
How many blocks are replaced? [2 points]
e) What is the hit ratio? [2 points]
f) List the final state of the cache, with each valid entry represented as a record of . [2 points]
Tag index offset 31-10 9-5 4-0Explanation / Answer
1. add $t0, $0, $0 # i = 0
L1: slt $t2, $t0, $s0 # i < a
beq $t2, $0, Exit # $t2 == 0, go to Exit
addi $t0, $t0, 1 # i = i+1
add $t1, $0, $0 # j = 0
L2: slt $t2, $t1, $s1 # j < b
beq $t2, $0, L1 # if $t2 == 0, go to L1
add $t2, $t0, $t1 # i+j
sll $t4, $t1, 4 # $t4 = 4*j (sll was written instead of mul.)
add $t3, $t4, $s2 # $t3 = &D[4*j]
sw $t2, 0($t3) # D[4*j] = i+j
addi $t1, $t1, 1 # j = j+1
j L2
Exit:
2.
a. Since 5 bits are used for the offset that implies
2^5=32 bytes= 8words
b. For this direct- mapped cache, Since 5 bits are used as the index it implies
2^5sets=32 entries
c. Total bits= 2^5(8*32data bits+22 tag bits+1valid bit)= 8928
data storage bits= 2^5*(8*32)=8192
Ratio = Total bits/data storage bits=8928/8192= 1.089
d. Block 0 is replaced 3 times & block 4 is replaced once. therefore, only 2 blocks are replaced.
e. 0 miss <00000, 0000, mem[0..31]>
4 hit <00000, 0000, mem[0..31]>
16 hit <00000, 0000, mem[0..31]>
132 miss <00100, 0000, mem[128..159]>
232 miss <00111, 0000, mem[224..255]>
160 miss <00101, 0000, mem[160..191]>
1024 miss <00000, 0001, mem[1024..1055]>
30 miss <00000, 0000, mem[0..31]>
140 hit <00100, 0000, mem[128..159]>
3100 miss <00000, 0011, mem[3072..3103]>
180 hit <00101, 0000, mem[160..191]>
2180 miss <00100, 0010, mem[2176..2207]>
As we can see there are four hits out of 12 accesses,
Hit Ratio = 4/12
so the hit rate should be 33%.
f.
Index Tag Data
0 0000 0000 0000 0000 0000 11 Mem(3072 – 3103)
3 0000 0000 0000 0000 0000 10 Mem(2176 – 2207)
5 0000 0000 0000 0000 0000 00 Mem(160-191)
7 0000 0000 0000 0000 0000 00 Mem(224-255)
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