Computer Architecture QUESTION 2 You are given a cache with a total data size of

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Computer Architecture

QUESTION 2 You are given a cache with a total data size of 16 words. Consider following 16 memory accesses (these are 6-bit word addresses) in this particular order. 0 4 5 16 17 2 3 0 1 18 19 89 16 17 In this question, you will analyze various configurations of this 16-word cache. For each configuration, specify whether each memory access is hit or miss, find out the total number of cache hits and misses and the final cache state (you do not need to specify tag and valid bits after these memory accesses. Assume that initially all cache entries are invalid and use LRU (least recently used replacement policy. a) In this part, assume that each block is one word. So, there are 16 blocks in cache. Configure the cache as i) Direct mapped (1-way set associative) ii 2-way set associative iii) 4-way set associative b) In this part, assume that each block is two words. So, there are 8 blocks in cache. Configure the cache as i) Direct mapped (1-way set associative) ii 2-way set associative iii) 4-way set associative

Explanation / Answer

Key points: Total data size of 16 words Problem Statement as short points: For each configuration, find 1) Whether each memory access is a HIT or MISS? 2) Find total cache HITS 3) Find total cache MISSES 4) Find final cache state after accessing memory (Tags and valid bits are not needed to be listed) Let initial cache entries = invalid Least Recently Used ( LRU ) Policy is used Cache Block = 1 word = 6 bits = less than a byte ( because 1 byte = 7+1 bits) Part a) of the question: Each block = 1 word = 6 bits hence 6 bits per block 16 words * 6 bits per word = 96 bits in total in cache Part b): Each block = 2 words = 12 bits Hence 12 bits per blocks Cache has 7+1 blocks

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