Computer Architecture Problem 2 [16 points] Consider a system with the following

Question

Computer Architecture

Problem 2 [16 points] Consider a system with the following processor components and policies: A direct-mapped L1 data cache of size 16KB and block size of 32 bytes, indexed and tagged using physical addresses, and using a write-allocate, write-back policy A fully-associative data TLB with 4 entries and an LRU replacement policy Physical addresses of 32 bits, and virtual addresses of 40 bits *Byte addressable memory Part A [2 points] Which bits of the virtual address are used to obtain a virtual to physical translation from the TLB? Page size of 1MB Explain exactly how these bits are used to make thetranslation, assuming there is a TLB hit Part B [2 points] Which bits of the virtual or physical address are used as the tag, index, and block offset bits for accessing the L1 data cache? Explicitly specify which of these bits can be used directly from the virtual address without any translation.

Explanation / Answer

Which bits of thevirtual address are used to obtain a virtual to physicaltranslation from

the TLB? Explainexactly how these bits are used to make the translation, assumingthere

is a TLBhit.

Solution

Thevirtual address is 40 bits long. Because the virtual page size is1MB = 2^20 bytes,

andmemory is byte addressable, the virtual page offset is 20 bits.Thus, the first 40-

20=20bits are used for address translation at the TLB. Since the TLB isfully associative,

all ofthese bits are used for the tag; i.e., there are no indexbits.

When avirtual address is presented for translation, the hardware firstchecks to see if the

20 bittag is present in the TLB by comparing it to all other entriessimultaneously. If a

validmatch is found (i.e., a TLB hit) and no protection violationoccurs, the page frame

number is readdirectly from the TLB.

Which bits of the virtual orphysical address are used as the tag, index, and blockoffset

bits for accessing the L1data cache? Explicitly specify which of these bits can beused

directly from the virtualaddress without any translation.

Solution

Since thecache is physically indexed and physically tagged, all of the bitsfrom accessing

the cachemust come from the physical address. However, since the lowest 20bits of the

virtualaddress form the page offset and are therefore not translated,these 20 bits can be

useddirectly from the virtual address. The remaining 12 bits (of thetotal of 32 bits in the

physicaladdress) must be used after translation.

Since theblock size is 16 bytes = 2^4 bytes, and memory is byte addressable,the lowest

4 bits areused as block offset.

Since thecache is direct mapped, the number of sets is 4KB/16 bytes = 2^8.Therefore, 8

bits areneeded for the index.

Theremaining 32-8-4 = 20 bits are needed for thetag.

20bits                       8bits                   4 bits

Tag                             Index                   Offset

As mentionedabove, the index and offset bits can be used before translationwhile the tag bits must await the translation for the 12 uppermostbits.

AnswerC:

The followingtable lists a stream of eight data loads and stores to virtualaddresses by the

processor (alladdresses are in hexadecimal). Complete the rest of the entries inthe table

corresponding tothese loads and stores using the above information and yoursolutions to

parts A and B. Forthe data TLB hit, data cache hit, and protection violationcolumns,

specify“yes” or “no.” Assume initially the dataTLB and data cache are bothempty.

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