In this exercise, we examine how pipelining affects the clock cycle time of the

ID: 3780706 • Letter: I

Question

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? What is the total latency of an LW instruction in a pipelined and non-pipelined processor? If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? Assuming there are no stalls or hazards, what is the utilization of the data memory? Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? Instead of a single-cycle organization, we can use multi-cycle

Explanation / Answer

4.8 It is given that:

MEM

250ps

350ps

150ps

300ps

200ps

And the instructions executed by the processor are broken down as:

Alu

Beq

45%

20%

15%

4.8.1. Basic Five Stage Pipelining: Clock cycle time

IF = Instruction Fetch,

ID = Instruction Decode,

EX = Execute,

MEM = Memory access,

WB = Register write back.

The Clock cycle time in pipelined and non-pipelined processor is:

Pipelining reduces the cycle time to the length of the longest stage and the register delay.

i.e., 1250/5+1250= 1500ns.

4.8.2 Total latency of an Lw instruction

LW instruction uses all 5 stages.

Pipelined processor takes 5 cycles at 0.2ps per cycle.

Non-pipelined processor takes 45+20+20+15 = 100ps.

4.8.3

Split Memory Access stage into two stages of 250ps. New clock cycle time is 250ps

4.8.4

LW and SW instructions use the data memory. As a result, the utilization of the data memory
is 20% + 15% = 35%.

4.8.5

ALU and LW instructions use the register block’s write port. As a result, the
utilization of the register block’s write port is 45% + 20% = 65%

4.8.6

Yes we can use multi cycle organization because the multi-cycle implementation could be as much as 1.27 times faster

MEM

250ps

350ps

150ps

300ps

200ps

Navigate

In this exercise, we examine how data dependencies affect execution in the basic

In this exercise, we examine how pipelining affects the clock cycle time of the

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.

In this exercise, we examine how pipelining affects the clock cycle time of the

Question

Explanation / Answer

Related Questions

Navigate