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In this exercise, we examine how data dependencies affect execution in the basic

ID: 3349523 • Letter: I

Question

In this exercise, we examine how data dependencies affect execution in the basic 5-stage pipeline described in Section 4.5. Problems in this exercise refer to the following sequence of instructions: Also, assume the following cycle times for each of the options related to forwarding: Without forwarding With Full forwarding 250ps 300ps

a) How many RAW data dependencies are there?

b) How many WAR data dependencies are there?

c) How many WAW data dependencies are there?

d) What is the total execution time of this instruction sequence without forwarding and with full forwarding?

7) In this exercise, we examine how data dependences affect execution in the basic 5-stage pipeline described in Section 4.5. Problems in this exercise refer to the following sequence of instructions: or rl,r2,r3 or r2,rl,r4 or rl,rl,r2 Also, assume the following cycle times for each of the options related to forwarding: Without forwarding 250ps With Full forwarding 300ps a) b) c) d) How many RAW data dependencies are there? How many WAR data dependencies are there? How many WAW data dependencies are there? What is the total execution time of this instruction sequence without forwarding and with full forwarding?

Explanation / Answer

a) RAW dependencies: For r1 in instruction 1 & 2 and 1 & 3. For r2 in instruction 2 & 3.

So there are 3 RAW dependencies

b) WAR dependencies: For r2 in instruction 1 & 2. For r1 in instruction 2 & 3 and in instruction 3

So there are 3 WAR dependencies

c) WAW dependencies: For r1 instruction 1 & 3.

The 5 stages in a pipeline are Instruction Fetch (IF), Instruction Decode (ID), Execute (Exec), Memory Access (Mem) and register write back (WB).

Without forwarding: The next instruction waits for previous instruction to be executed.

1

2

3

4

5

6

7

8

9

10

11

Or r1, r2, r3

IF

ID

Exec

Mem

WB

or r2, r1, r4

IF

ID

-

-

Exec

Mem

WB

or r1, r1, r2

IF

ID

-

-

-

-

Exec

Mem

WB

Total 11 cycles .

Time taken = 11 X 250ps = 2750ps

With forwarding: The next instruction does not wait for previous instruction to be executed.

1

2

3

4

5

6

7

Or r1, r2, r3

IF

ID

Exec

Mem

WB

or r2, r1, r4

IF

ID

Exec

Mem

WB

or r1, r1, r2

IF

ID

Exec

Mem

WB

Total 7 cycles .

Time taken = 7 X 300ps = 2100ps

1

2

3

4

5

6

7

8

9

10

11

Or r1, r2, r3

IF

ID

Exec

Mem

WB

or r2, r1, r4

IF

ID

-

-

Exec

Mem

WB

or r1, r1, r2

IF

ID

-

-

-

-

Exec

Mem

WB

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